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The Impact of Externally Applied Mechanical Stress on Analog and RF Performances of SOI MOSFETs

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Języki publikacji
EN
Abstrakty
EN
This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also ex- tracted as a function of applied mechanical stress. Piezoresistance coefficientis shown to be a key element in describing the enhancement in the characteristics of the device due to mechanical stress.
Rocznik
Tom
Strony
18--24
Opis fizyczny
Bibliogr. 22 poz., rys.
Twórcy
autor
autor
autor
  • Universit´e catholique de Louvain, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium, mostafa.emam@uclouvain.be
Bibliografia
  • [1] V. Chan, K. Rim, M. Ieong, S. Yang, R. Malik, Y. W. Teh, M. Yang, and Q. C. Ouyang, “Strain for CMOS performance improvement”, in Proc. IEEE Custom Integr. Circ. Conf., San Jose, USA, 2005, pp. 667–673.
  • [2] D. V. Singh, K. A. Jenkins, J. Sleight, Z. Ren, M. Ieong, and W. Haensch, “Strained ultrahigh performance fully depleted nMOSFETs with ft of 330 GHz and sub-30 nm gate lengths”, IEEE Electron Dev. Lett., vol. 27, no. 3, pp. 191–193, 2006.
  • [3] S. Houri, M. Emam, and J.-P. Raskin, “RF behavior of strained fully depleted SOI MOSFETs”, in Proc. EUROSOI Conf., Cork, Ireland, 2008, pp. 55–56.
  • [4] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, “A new aspect of mechanical stress effects in scaled MOS devices”, IEEE Electron Dev. Lett., vol. 38, no. 4, pp. 895–900, 1991.
  • [5] C.-L. Huang, H. R. Soleimani, G. J. Grula, J. W. Sleight, A. Villani, H. Ali, and D. A. Antoniadis, “LOCOS-induced stress effects on thin-film SOI devices”, IEEE Trans. Electron Dev., vol. 44, no. 4, pp. 646–650, 2004.
  • [6] R. Degraeve, G. Groeseneken, I. De Wolf, and H. E. Maes, “The effect of externally imposed mechanical stress on the hot-carrierinduced degradation of deep-sub micron nMOSFET’s”, IEEE Trans. Electron Dev., vol. 44, no. 6, pp. 943–950, 1997.
  • [7] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress”, IEEE Trans. Electron Dev., vol. 51, no. 8, pp. 1254–1261, 2004.
  • [8] S. E. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu, and T. Nishida, “Future of strained Si/semiconductors in nanoscale MOSFETs”, in Proc. Int. Electron Dev. Meet. IEDM, San Francisco, USA, 2006, pp. 1–4.
  • [9] F. Rochette, M. Cass´e, M. Mouis, G. Reimbold, D. Blachier, C. Leroux, B. Guillaumot, and F. Boulanger, “Experimental evidence and extraction of the electron mass variation in [110] uniaxially strained MOSFETs”, Solid-State Electron., vol. 51, no. 11-12, pp. 1458–1465, 2007.
  • [10] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (∼1.5 GPa) channel stress”, IEEE Electron Dev. Lett., vol. 28, no. 1, pp. 58–61, 2007.
  • [11] Y. S. Choi, T. Numata, T. Nishida, R. Harris, and S. E. Thompson, “Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function”, J. Appl. Phys., vol. 103, no. 64510, pp. 1–5, 2008.
  • [12] J.-S. Lim, A. Acosta, S. E. Thompson, G. Bosman, E. Simoen, and T. Nishida, “Effect of mechanical strain on 1/ f noise in metaloxide semiconductor field-effect transistors”, J. Appl. Phys., vol. 105, no. 54504, pp. 1–11, 2009.
  • [13] Y. J. Kuo, T. C. Chang, P. H. Yeh, S. C. Chen, C. H. Dai, C. H. Chao, T. F. Young, O. Cheng, and C. T. Huang, “Substrate current enhancement in 65 nm metal-oxide-silicon field-effect transistor under external mechanical stress”, Thin-Solid Films, vol. 517, no. 5, pp. 1715–1718, 2009.
  • [14] D. Colman, R. T. Bate, and J. P. Mize, “Mobility anisotropy and piezoresistance in silicon p-type inversion layers”, J. Appl. Phys., vol. 39, no. 4, pp. 1923–1931, 1968.
  • [15] G. Dorda, “Piezoresistance in quantized conduction bands in silicon inversion layers”, J. Appl. Phys., vol. 42, no. 5, pp. 2053–2060, 1971.
  • [16] B. Borchert and G. E. Dorda, “Hot-electron effects on short-channel MOSFET’s determined by the piezoresistance effect”, IEEE Trans. Electron Dev., vol. 35, no. 4, pp. 483–488, 1988.
  • [17] D. Flandre, J.-P. Eggermont, D. De Ceuster, and P. Jespers, “Comparison of SO1 versus bulk performances of CMOS micropower singlestage OTAs”, IEEE Electron. Lett., vol. 30, no. 23, pp. 1933–1934, 1994.
  • [18] S. M. Sze, Semiconductor Devices Physics and Technology. New York: Wiley, 1985.
  • [19] G. Dambrine, C. Raynaud, D. Lederer, M. Dehan, O. Rozeaux, M. Vanmackelberg, F. Danneville, S. Lepilliet, and J.-P. Raskin, “What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?”, IEEE Electron Dev. Lett., vol. 24, no. 3, pp. 189–191, 2003.
  • [20] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker-Janvier, and J.-P. Colinge, “Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling”, IEEE Trans. Electron Dev., vol. 45, no. 5, pp. 1017–1025, 1998.
  • [21] A. Bracale et al., “A new approach for SOI devices small-signal parameters extraction”, Anal. Integr. Circ. Sig. Process., vol. 25, no. 2, pp. 157–169, 2000.
  • [22] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon”, IEEE Trans. Electron Dev., vol. ED-29, no. 1, pp. 64–70, 1982.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BATA-0008-0002
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