SOI Technology: An Opportunity for RF Designers?

• Autorzy: Raskin J.-P.
• Języki publikacji: EN

Abstrakty

EN

This last decade silicon-on-insulator (SOI) MOS-FET technology has demonstrated its potentialities for high frequency (reaching cutoff frequencies close to 500 GHz for n-MOSFETs) and for harsh environments (high temperature, radiation) commercial applications. For RF and system-onchip applications, SOI also presents the major advantage of providing high resistivity substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 k? cm can easily be achieved and high resistivity silicon (HRS) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications. In this paper, based on several experimental and simulation results the interest, limitations but also possible future improvements of the SOI MOS technology are presented.

Słowa kluczowe

EN

crosstalk; high resistivity silicon substrate; MOSFET; nonlinearities; silicon-on-insulator; wideband characterization

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2009
• Tom: nr 4
• Strony: 3--17
• Opis fizyczny: Bibliogr. 79 poz., rys., tab.

Twórcy

autor

Raskin J.-P.

• Université catholique de Louvain, Microwave Laboratory, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium,

Bibliografia

• [1] G. E.Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, pp. 114–117, 1965.
• [2] R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET’s with very small physical dimensions”, IEEE J. Solid-State Circ., vol. SC-9, pp. 256–268, 1974.
• [3] S. Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, J. Kim, J.-O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS technology”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 2007, Washington, USA, 2007, pp. 255–258.
• [4] T. Sakurai, A. Matsuzawa, and T. Douseki, Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications. New Jersey: Springer, 2006.
• [5] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology”, IEEE Trans. Electron Dev., vol. 44, no. 12, pp. 2252–2261, 1997.
• [6] H. F. Cooke, “Microwave transistors: theory and design”, Proc. IEEE, vol. 59, pp. 1163–1181, 1971.
• [7] C. A. Mead, “Schottky barrier gate field effect transistor”, Proc. IEEE, vol. 59, pp. 307–308, 1966.
• [8] W. Baechtold, K. Daetwyler, T. Forster, T. O. Mohr, W. Walter, and P. Wolf, “Si and GaAs 0.5 μm gate Schottky-barrier field-effect transistors”, Electron. Lett., vol. 9, pp. 232–234, 1973.
• [9] T. Mimura, S. Hiyamizu, T. Fujii, and K. Nanbu, “A new field-effect transistor with selectively doped GaAs/n-AlxGa1−xAs heterojunctions”, Jpn. J. Appl. Phys., vol. 19, pp. L225–L227, 1980.
• [10] P. M. Smith, S.-M. J. Liu, M.-Y. Kao, P. Ho, S. C. Wang, K. H. G. Duh, S. T. Fu, and P. C. Chao, “W-band high efficiency InP-based power HEMT with 600 GHz fmax”, IEEE Microw. Guid. Wave Lett., vol. 5, no. 7, pp. 230–232, 1995.
• [11] M. J. W. Rodwell, M. Urteaga, T. Mathew, D. Scott, D. Mensa, Q. Lee, J. Guthrie, Y. Betser, S. C. Martin, R. P. Smith, S. Jaganathan, S. Krishnan, S. I. Long, R. Pullela, B. Agarwal, U. Bhattacharya, L. Samoska, and M. Dahlstrom, “Submicron scaling of HBTs”, IEEE Trans. Electron Dev., vol. 48, pp. 2606–2624, 2001.
• [12] R. Lai, X. B. Mei, W. R. Deal, W. Yoshida, Y. M. Kim, P. H. Liu, J. Lee, J. Uyeda, V. Radisic, M. Lange, T. Gaier, L. Samoska, and A. Fung, “Sub 50 nm InP HEMT device with fmax greater than 1 THz”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 2007, Washington, USA, 2007, pp. 609–611.
• [13] H. S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, I. Saito, T. Morimoto, Y. Katsumata, and H. Iwai, “High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 1996, San Francisco, USA, 1996, pp. 105–108.
• [14] “International Technology Roadmap for Semiconductors”, 2006, [Online]. Available: http://www.itrs.net/Common/2006ITRS/ Home2006.html
• [15] G. Dambrine, C. Raynaud, D. Lederer, M. Dehan, O. Rozeaux, M. Vanmackelberg, F. Danneville, S. Lepilliet, and J.-P. Raskin, “What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?”, IEEE Electron Dev. Lett., vol. 24, no. 3, pp. 189–191, 2003.
• [16] G. Pailloncy, C. Raynaud, M. Vanmackelberg, F. Danneville, S. Lepilliet, J.-P. Raskin, and G. Dambrine, “Impact of down scaling on high frequency noise performance of bulk and SOI MOSFETs”, IEEE Trans. Electron Dev., vol. 51, no. 10, pp. 1605–1612, 2004.
• [17] V. Kilchytska, A. N`eve, L. Vancaillie, D. Levacq, S. Adriaensen, H. van Meer, K. De Mayer, C. Raynaud, M. Dehan, J.-P. Raskin, and D. Flandre, “Influence of device engineering on the analog and RF performances of SOI MOSFETs”, IEEE Trans. Electron Dev., vol. 50, no. 3, pp. 577–588, 2003.
• [18] M. Vanmackelberg, C. Raynaud, O. Faynot, J.-L. Pelloie, C. Tabone, A. Grouillet, F. Martin, G. Dambrine, L. Picheta, E. Mackowiak, P. Llinares, J. Sevenhans, E. Compagne, G. Fletcher, D. Flandre, V. Dessard, D. Vanhoenacker, and J.-P. Raskin, “0.25 μm fullydepleted SOI MOSFET’s for RF mixed analog-digital circuits, including a comparison with partially-depleted devices for high frequency noise parameters”, Solid-State Electron., vol. 46, iss. 3, pp. 379–386, 2002.
• [19] S. Burignat, D. Flandre, V. Kilchytska, F. Andrieux, O. Faynot, and J.-P. Raskin, “Substrate impact on sub-32 nm ultra thin SOI MOSFETs with thin buried oxide”, in Proc EUROSOI 2009, Fifth Worksh. Them. Netw. Sil. Insul. Technol. Dev. Circ., Göteborg, Sweden, 2009, pp. 27–28.
• [20] T. Rudenko, V. Kilchytska, S. Burignat, J.-P. Raskin, F. Andrieu, O. Faynot, A. Nazarov, and D. Flandre, “Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX”, in Proc. EUROSOI 2009, Fifth Worksh. Them. Netw. Sil. Insul. Technol. Dev. Circ., Göteborg, Sweden, 2009, pp. 111–112.
• [21] K.-W. Ang, J. Lin, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo, “Strained n-MOSFET with embedded source/drain stressors and strain-transfer structure (STS) for enhanced transistor performance”, IEEE Trans. Electron Dev., vol. 55, no. 3, pp. 850–857, 2008.
• [22] G. Néau, F. Martinez, M. Valenza, J. C. Vildeuil, E. Vincent, F. Boeuf, F. Payet, and K. Rochereau, “Impact of strained-channe n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements”, Microelectron. Reliab., vol. 47, pp. 567–572, 2007.
• [23] S. H. Olsen, E. Escobedo-Cousin, J. B. Varzgar, R. Agaiby, J. Seger, P. Dobrosz, S. Chattopadhyay, S. J. Bull, A. G. O’Neill, P.-E. Hellstrom, J. Edholm, M. Ostling, K. L. Lyutovich, M. Oehme, and E. Kasper, “Control of self-heating in thin virtual substrate strained Si MOSFETs”, IEEE Trans. Electron Dev., vol. 53, no. 9, pp. 2296–2305, 2006.
• [24] J. M. Larson and J. Snyder, “Overview and status of metal S/D Schottky barrier MOSFET technology”, IEEE Trans. Electron Dev., vol. 53, no. 5, pp. 1048–1058, 2006.
• [25] D. J. Pearman, G. Pailloncy, J.-P. Raskin, J. M. Larson, and T. E. Whall, “Static and high-frequency behavior and performance of Schottky barrier p-MOSFET devices”, IEEE Trans. Electron Dev., vol. 54, no. 10, pp. 2796–2802, 2007.
• [26] J.-P. Raskin, D. J. Pearman, G. Pailloncy, J. M. Larson, J. Snyder, D. L. Leadley, and T. E. Whall, “High-frequency performance of Schottky barrier p-MOSFET devices”, IEEE Electron Dev. Lett., vol. 29, no. 4, pp. 396–398, 2008.
• [27] G. Larrieu, E. Dubois, R. Valentin, N. Breil, F. Danneville, G. Dambrine, J.-P. Raskin, and J.-C. Pesant, “Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 2007, Washington, USA, 2007, pp. 147–150.
• [28] R. Valentin, E. Dubois, J.-P. Raskin, G. Larrieu, G. Dambrine, T. C. Lim, N. Breil, and F. Danneville, “RF small signal analysis of Schottky-barrier p-MOSFET”, IEEE Trans. Electron Dev., vol. 55, no. 5, pp. 1192–1202, 2008.
• [29] B. Ricco, R. Versari, and D. Esseni, “Characterization of polysilicongate depletion in MOS structures”, IEEE Electron Dev. Lett., vol. 17, no. 3, pp. 103–105, 1996.
• [30] A. Vandooren, A. V. Y. Thean, Y. Du, I. To, J. Hughes, T. Stephens, M. Huang, S. Egley, M. Zavala, K. Sphabmixay, A. Barr, T. White, S. Samavedam, L. Mathew, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, B.-Y. Nguyen, B. White, M. Orlowski, A. Duvallet, T. Dao, and J. Mogab, “Mixed-signal performance of sub-100 nm fully-depleted SOI devices with metal gate, high K (HfO2) dielectric and elevated source/drain extensions”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 2003, Washington, USA, 2003, pp. 11.5.1–11.5.3.
• [31] C. H. Ko, T. M. Kuan, K. Zhang, G. Tsai, S. M. Seutter, C. H. Wu, T. J. Wang, C. N. Ye, H. W. Chen, C. H. Ge, K. H. Wu, and W. C. Lee, “A novel CVD-SiBCN low-K spacer technology for high-speed applications”, in Proc. Int. Symp. VLSI Technol. 2008, Honolulu, Hawaii, USA, 2008, pp. 108–109.
• [32] T. I. Bao, H. C. Chen, C. J. Lee, H. H. Lu, S. L. Shue, and C. H. Yu, “Low capacitance approaches for 22 nm generation Cu interconnect”, in Proc. Int. Symp. VLSI Technol. Syst. Appl. VLSI-TSA 2009, Hsinchu, Taiwan, 2009, pp. 51–56.
• [33] T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, “Fringing fields in sub-0.1 μm fully depleted SOI MOSFET’s: optimization of the device architecture”, Solid-State Electron., vol. 46, pp. 373–378, 2002.
• [34] M. Fujiwara et al., “Impact of BOX scaling on 30 nm gate length FD SOI MOSFET”, IEEE Int. SOI Conf., Honolulu, Hawaii, USA, 2005, pp. 180–182.
• [35] F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, C. Clement, P. Benech, J. M. Fournier, and G. Dambrine, “State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on high resistivity substrate”, in Proc. IEEE Int. SOI Conf., Niagara Falls, USA, 2006, pp. 121–122.
• [36] F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, and P. Touret, “On the design of high performance RF integrated inductors on high resistively thin film 65 nm SOI CMOS technology”, in Proc. IEEE 8th Top. Meet. Sil. Monolit. Integr. Circ. RF Syst. SiRF 2008, Orlando, USA, 2008, pp. 98–101.
• [37] I. Post, M. Akbar, G. Curello, S. Gannavaram, W. Hafez, U. Jalan, K. Komeyii, J. Lin, N. Lindert, J. Park, J. Rizk, G. Sacks, C. Tsai, D. Yeh, P. Bai, and C.-H. Jan, “A 65 m CMOS SOC technology featuring strained silicon transistors for RF applications”, in Proc. Int. Electron Dev. Meet. IEDM 2006, San Francisco, USA, 2006, pp. 1–3.
• [38] J.-P. Colinge, M.-H. Gao, A. Romano, H. Maes, and C. Claeys, “Silicon-on-insulator “gate-all-around” MOS device”, in Proc. IEEE SOS/SOI Tech. Conf., Key West, USA, 1990, pp. 137–138.
• [39] D. Hisamoto et al., “FinFET – a self-aligned double-gate MOSFET scalable to 20 nm”, IEEE Trans. Electron Dev., vol. 47, no. 12, pp. 2320–2325, 2000.
• [40] S. Cristoloveanu, “Silicon on insulator technologies and devices: from present to future”, Solid-State Electron., vol. 45, no. 8, pp. 1403–1411, 2001.
• [41] J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines”, IEEE Trans. Electron Dev., vol. 49, no. 12, pp. 2222–2229, 2002.
• [42] J. Kedzierski et al., “High performance symmetric-gate and CMOScompatible Vt asymmetric-gate FinFET devices”, in Proc. IEEE Int. Electron Dev. Meet. IEDM 2001, Washington, USA, 2001, pp. 437–440.
• [43] D. Woo et al., “Electrical characteristics of FinFET with vertically nonuniform source/drain profile”, IEEE Trans. Nanotech., vol. 1, no. 4, pp. 233–237, 2002.
• [44] V. Kilchytska, N. Collaert, R. Rooyackers, D. Lederer, J.-P. Raskin, and D. Flandre, “Perspective of FinFETs for analog applications”, in Proc. 34th Eur. Solid-State Dev. Res. Conf. ESSDERC 2004, Leuven, Belgium, 2004, pp. 65–68.
• [45] D. Lederer et al., “FinFet analogue characterization from DC to 110 GHz”, Solild-State Electron., vol. 49, pp. 1488–1496, 2005.
• [46] A. Dixit et al., “Analysis of the parasitic source/drain resistance in multiple gate field effect transistors”, IEEE Trans. Electron Dev., vol. 52, no. 6, pp. 1131–1140, 2005.
• [47] J. P. Raskin et al., “Accurate MOSFET characterization at microwaver frequencies for device optimization and analog modeling”, IEEE Trans. Electron Dev., vol. 45, pp. 1017–1025, 1998.
• [48] A. Bracale et al., “A new approach for SOI device small-signal parameter extraction”, Analog Integr. Circ. Sig. Process., vol. 25, pp. 159–167, 2000.
• [49] B. Razavi, R.-H. Yan, and K. F. Lee, “Impact of distributed gate resistance on the performance of MOS devices”, IEEE Trans. Circ. Syst. I: Fund. Theory Appl., vol. 41, no. 11, pp. 750–754, 1994.
• [50] W. Wu and M. Chan, “Analysis of geometry-dependent parasitics in multifin double-gate FinFETs”, IEEE Trans. Electron Dev., vol. 54, no. 4, pp. 692–698, 2007.
• [51] O. Moldovan, D. Lederer, B. Iniguez, and J.-P. Raskin, “Finite element simulations of parasitic capacitances related to multiple-gate field-effect transistors architectures”, in Proc. 8th Top. Meet. Sil. Monolit. Integr. Circ. RF Syst. SiRF 2008, Orlando, USA, 2008, pp. 183–186.
• [52] J.-P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre, “Analog/RF performance of multiple-gate SOI devices: wideband simulations and characterization”, IEEE Trans. Electron Dev., vol. 53, no. 5, pp. 1088–1094, 2006.
• [53] J.-P. Raskin, G. Pailloncy, D. Lederer, F. Danneville, G. Dambrine, S. Decoutere, A. Mercha, and B. Parvais, “High frequency noise performance of 60 nm gate length FinFETs”, IEEE Trans. Electron Dev., vol. 55, no. 10, pp. 2718–2727, 2008.
• [54] F. Gianesello et al., “1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS technology”, in Proc. Conf. IEEE MTT-S, Honolulu, Hawaii, USA, 2007.
• [55] D. Lederer and J.-P. Raskin, “Effective resistivity of fully-processed high resistivity wafers”, Solid-State Electron., vol. 49, pp. 491–496, 2005.
• [56] W. Heinrich, “Quasi-TEM description of MMIC coplanar lines including conductor-loss effects”, IEEE Trans. Microw. Theory Tech., vol. 41, no. 1, pp. 45–52, 1993.
• [57] A. C. Reyes, S. M. El-Ghazaly, S. J. Dom, M. Dydyk, D. K. Schroeder, and H. Patterson, “Coplanar waveguides and microwave inductors on silicon substrates”, IEEE Trans. Microw. Theory Tech., vol. 43, no. 9, pp. 2016–2021, 1995.
• [58] K. Benaissa, J.-T. Yuan, D. Crenshaw, B. Williams, S. Sridhar, J. Ai, G. Boselli, S. Zhao, S. Tang, S. Ashbun, P. Madhani, T. Blythe, N. Mahalingam, and H. Schichijo, “RF CMOS high-resistivity substrates for systems-on-chip applications”, IEEE Trans. Electron Dev., vol. 50, no. 3, pp. 567–576, 2003.
• [59] Y. Wu, H. S. Gamble, B. M. Armstrong, V. F. Fusco, and J. A. C. Stewart, “SiO2 interface layer effects on microwave loss of high-resistivity CPW line”, IEEE Microw. Guid. Wave Lett., vol. 9, no. 1, pp. 10–12, 1999.
• [60] D. Lederer, C. Desrumeaux, F. Brunier, and J.-P. Raskin, “High resistivity SOI substrates: how high should we go?”, in Proc. IEEE Int. SOI Conf., Newport Beach, USA, 2003, pp. 50–51.
• [61] C. Schollhorn, W. Zhao, M. Morschbach, and E. Kasper, “Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon”, IEEE Trans. Electron Dev., vol. 50, no. 3, pp. 740–746, 2003.
• [62] H.-C. Lu and T.-H. Chu, “The thru-line-symmetry (TLS) calibration method for on-wafer scattering matrix measurement of four-port networks”, in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Ford Worth, USA, 2004, vol. 3, pp. 1801–1804.
• [63] H. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, “Low-loss CPW lines on surface stabilized high resistivity silicon”, IEEE Microw. Guid. Wave Lett., vol. 9, no. 10, pp. 395–397, 1999.
• [64] B. Wong, J. N. Burghartz, L. K. Natives, B. Rejaei, and M. van der Zwan, “Surface-passivated high resistivity silicon substrates tor RFICs”, IEEE Electron Dev. Lett., vol. 25, no. 4, pp. 176–178, 2004.
• [65] D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity”, IEEE Electron Dev. Lett., vol. 26, no. 11, pp. 805–807, 2005.
• [66] F. Calmon, C. Andrei, O. Valorge, J.-C. Nunez Perez, J. Verdier, and C. Gontrand, “Impact of low-frequency substrate disturbances on a 4.5 GHz VCO”, Microelectron. J., vol. 37, no. 1, pp. 1119–1127, 2006.
• [67] M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsen, “High-level simulation of substrate noise generation including power supply noise coupling”, in Proc. 37th Conf. Des. Automat. DAC 2000, Los Angeles, USA, 2000, pp. 446–451.
• [68] D. Lederer and J.-P. Raskin, “Bias effects on RF passive structures in HR Si substrates”, in Proc. 6th Top. Meet. Sil. Microw. Integr. Circ. RF Syst., San Diego, USA, 2006, pp. 8–11.
• [69] M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. G. E. Engels, and I. Bolsens, “Analysis and experimental verification of digital substrate noise generation for epi-type substrates”, IEEE J. Solid-State Circ., vol. 35, no. 7, pp. 1002–1008, 2000.
• [70] M. van Heijningen, M. Badaroglu, S. Donnay, G. G. E. Gielen, and H. J. De Man, “Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification”, IEEE J. Solid-State Circ., vol. 37, no. 8, pp. 1065–1072, 2002.
• [71] M. Badaroglu, S. Donnay, H. J. De Man, Y. A. Zinzius, G. G. E. Gielen, W. Sansen, T. Fonden, and S. Signell, “Modeling and experimental verification of substrate noise generation in a 220-k gates WLAN system-on-chip with multiple supplies”, IEEE J. Solid-State Circ., vol. 38, no. 7, pp. 1250–1260, 2003.
• [72] K. A. Jenkins, W. Rhee, J. Liobe, and H. Ainspan, “Experimental analysis of the effect of substrate noise on PLL”, in Proc. 6th Top. Meet. Sil. Monolit. Integr. Circ. RF Syst., San Diego, USA, 2006, pp. 54–57.
• [73] “International Technology Roadmap for Semiconductors: Front end processes”, 2005 [Online]. Available: http://www.itrs.net/Common/2005ITRS/FEP2005.pdf
• [74] C. Roda Neve, D. Bol, R. Ambroise, D. Flandre, and J.-P. Raskin, “Comparison of digital substrate noise in SOI and bulk Si CMOS technologies”, in Proc. 7th Worksh. Low-Volt. Low Power Des., Louvain-la-Neuve, Belgium, 2008, pp. 23–28.
• [75] D. Bol, R. Ambroise, C. Roda Neve, J.-P. Raskin, and D. Flandre, “Wide-band simulation and characterization of digital substrate noise in SOI technology”, in Proc. IEEE Int. SOI Conf., Indian Wells, USA, 2007, pp. 133–134.
• [76] H. H. Chen and D. D. Ling, “Power supply noise analysis methodology for deep-submicron VLSI chip design”, in Proc. 34th Des. Automat., Anaheim, USA, 1997, pp. 638–643.
• [77] C. Tinella, O. Richard, A. Cathelin, F. Reaute, S. Majcherczak, F. Blanchet, and D. Belot, “0.13 μm CMOS SOI SP6T antenna switch for multi-standard handsets”, in Proc. 6th Top. Meet. Sil. Monolit. Integr. Circ. RF Syst., San Diego, USA, 2006, p. 58.
• [78] T. G. McKay, M. S. Carroll, J. Costa, C. Iversen, D. C. Kerr, and Y. Remoundos, “Linear cellular antenna switch for highly integrated SOI front-end”, in Proc. IEEE Int. SOI Conf., Indian Wells, USA, 2007.
• [79] “Single-pole four-throw high-power switch”, RF1450 Data sheet [Online]. Available: http://www.rfmd.com/pdfs/1450DS.pdf