Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support

• Autorzy: Łuczak A. , Stępniewski M. , Siast J. , Domański M. , Stankiewicz O. , Kurc M. , Konieczny J.
• Języki publikacji: EN

Abstrakty

EN

This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.

Słowa kluczowe

EN

debugging; FPGA; multi-chip; video coding

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2011
• Tom: nr 3
• Strony: 81--86
• Opis fizyczny: Bibliogr. 18 poz., rys.

Twórcy

autor

Łuczak A.

autor

Stępniewski M.

autor

Siast J.

autor

Domański M.

autor

Stankiewicz O.

autor

Kurc M.

autor

Konieczny J.

• Chair of Multimedia Telecommunications and Microelectronics, Faculty of Electronics and Telecommunications, Poznań University of Technology, Polanka st 3, 60-965 Poznań, Poland,

Bibliografia

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• [16] A. Łuczak and J. Siast, “Network-on-chip with multicast transsmition support”, to be published.
• [17] A. Łuczak, M. Stępniewska, and J. Siast, “Hierarchical addressing with hot-plug support in Network-on-Multi-Chip”, to be published.
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