Impact of Crosstalk into High Resistivity Silicon Substrate on the RF Performance of SOI MOSFET

• Autorzy: Ali K. B. , Neve C. R. , Gharsallah A. , Raskin J. P.
• Języki publikacji: EN

Abstrakty

EN

Crosstalk propagation through silicon substrate is a serious limiting factor on the performance of the RF devices and circuits. In this work, substrate crosstalk into high resistivity silicon substrate is experimentally analyzed and the impact on the RF behavior of silicon-on-insulator (SOI) MOS transistors is discussed. The injection of a 10 V peak-to-peak single tone noise signal at a frequency of 3 MHz ( fnoise) generates two sideband tones of ?56 dBm separated by fnoise from the RF output signal of a partially depleted SOI MOSFET at 1 GHz and 4.1 dBm. The efficiency of the introduction of a trap-rich polysilicon layer located underneath the buried oxide (BOX) of the high resistivity (HR) SOI wafer in the reduction of the sideband noise tones is demonstrated. An equivalent circuit to model and analyze the generation of these sideband noise tones is proposed.

Słowa kluczowe

EN

crosstalk; high resistivity Si; mixing products; passivation layer; polysilicon

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2010
• Tom: nr 4
• Strony: 93--100
• Opis fizyczny: Bibliogr. 11 poz., rys.

Twórcy

autor

Ali K. B.

autor

Neve C. R.

autor

Gharsallah A.

autor

Raskin J. P.

• Université catholique de Louvain, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium,

Bibliografia

• [1] International Technology Roadmap for Semiconductor (ITRS). 2007 Edition.
• [2] O. Rozeau, J. Jomaah, S. Haendler, J. Boussey, and F. Balestra, “SOI technologies overview for low power low voltage radio frequency applications”, Analog Integr. Circ. Sign. Proc., vol. 25, pp. 93–114, 2000.
• [3] H. Xiao, R. Huang, J. Liang, H. Liu, Y. Tian, R. Wang, and Y. Wang, “The localized-SOI MOSFET as a candidate for analog/ RF applications”, IEEE Trans. Electron Dev., vol. 54, no. 8, pp. 1978–1984, 2007.
• [4] H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, “Low-loss CPW on surface stabilized high-resistivity silicon”, IEEE Microw. Guid. Wave Lett., vol. 9, no. 10, pp. 395–297, 1999.
• [5] D. Lederer and J.-P. Raskin, “Substrate loss mechnisms for microstrip and CPW transmission lines on lossy silicon wafers”, Solid- State Electron., vol. 47, pp. 1927–1936, 2003.
• [6] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P.Colinge, “Substrate crosstalk reduction using SOI technology”, IEEE Trans. Electron Dev., vol. 44, no. 12, pp. 2252–2261, 1997.
• [7] D. Lederer, J.-P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate”, IEEE Trans. Electron Dev., vol. 55, no. 7, pp. 1664–1671, 2008.
• [8] Y. H. Wu, A. Chin, K. H. Shih, C. C. Wu, C. P. Liao, S. C. Pai, and C. C. Chi, “RF loss and crosstalk on extremely high resistivity (10 k – 1 MWcm) Si fabricated by ion implantation”, IEEE MTT-S Digest, 2000.
• [9] B. Rong, J. N. Burghartz, L. K. Nanver, B. Rejaei, and M. Van der Zwan, “Surface-passivated high resistivity silicon substrates for RFICs”, IEEE Electron Dev. Lett., vol. 25, no. 4, pp. 176–178, 2004.
• [10] D. Lederer, “WideBand characterization of advanced SOI material and MOS devices for high frequency applications”, Ph.D. thesis, UCL, Louvain-la-Neuve, Belgium, October 2006.
• [11] D. Lederer and J.-P. Raskin, “Effective resistivity of fully-processed SOI substrates”, Solid-State Electron., vol. 49, no. 3, pp. 491–496, 2005.