Optical interconnections in future VLSI systems

• Autorzy: Tosik G. , Lisik Z. , Gaffiot F.
• Języki publikacji: EN

Abstrakty

EN

This paper is focused on the latency and power dissipation in clock systems, which should be lower when the optical interconnects are applied. Simulation shows that the power consumed by an optical system is lower than that consumed by an electrical one, however the advantages of optics drastically decrease with the number of output nodes in H-tree. Additionally, simple replacement of an electrical system by an optical clock distribution network (CDN) results in high clock skew, which will be higher than 10% of the clock period for the 32 nm technology node.

Słowa kluczowe

EN

optical interconnects; clock skew; clock distribution network; OCDN; OVLSI

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 3
• Strony: 105--108
• Opis fizyczny: Bibliogr.6 poz., il.

Twórcy

autor

Tosik G.

autor

Lisik Z.

autor

Gaffiot F.

• Institute of Electronics, Technical University of Łodź, Wolczańska st 211, 90-924 Łodź, Poland,

Bibliografia

• [1] International Technology Roadmap of Semiconductors, 2005, http://www.itrs.net/Links/2005ITRS/Home2005.htm
• [2] S. Tam et al., “Clock generation and distribution for the first IA-64 microprocessor”, IEEE J. Solid-State Circ., vol. 35, no. 11, pp. 1545–1552, 2000.
• [3] A. Sakai et al., “Propagation characteristics of ultrahigh-D optical waveguide on silicon-on-insulator substrate”, Jpn. J. Appl. Phys., part 2, vol. 40, pp. 383–385, 2001.
• [4] G. Tosik et al., “Metallic clock distribution networks in new VLSI technologies”, IEE Electron. Lett., vol. 40, no. 3, pp. 198–200, 2004.
• [5] G. Tosik et al., “Optical versus electrical interconnections for clock distribution networks in new VLSI technologies”, Integrated Circuit and System Design Lecture Notes in Computer Science, vol. 2799, pp. 461–470, 2003.
• [6] F. J. Pollack, “New microarchitecture challenges in the coming generations of CMOS process technologies”, in Proc. 32nd Ann. ACM/IEEE Int. Symp. Microarchit., Haifa, Israel, 1999, pp. 2–4.