The influence of yield model parameters on the probability of defect occurrence

• Autorzy: Rakowski M. , Pleskacz W. A.
• Języki publikacji: EN

Abstrakty

EN

This paper describes the analysis of the influence of yield loss model parameters on the calculation of the probability of arising shorts between conducting paths in IC's. The characterization of the standard cell in AMS 0.8 žm CMOS technology is presented as well as obtained probability results and estimations of yield loss by changing values of model parameters.

Słowa kluczowe

EN

yield model parameters; spot defect; probability of defect occurrence; critical area

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 3
• Strony: 101--104
• Opis fizyczny: Bibliogr.5 poz., il., tab.

Twórcy

autor

Rakowski M.

autor

Pleskacz W. A.

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology Koszykowa st 75, 00-662 Warsaw, Poland,

Bibliografia

• [1] R. Ubar, W. Kuzmicz, W. Pleskacz, and J. Raik, “Defect-oriented fault simulation and test generation in digital circuits”, in Proc. ISQED Conf., San Jose, USA, 2001, pp. 365–371.
• [2] M. Blyzniuk, W. A. Pleskacz, M. Lobur, and W. Kuzmicz, “Estimation of the usefulness of test vector components for detecting faults resulting from shorts in standard cells”, in Proc. 7th Int. Conf. MIXDES, Gdynia, Poland, 2000, pp. 527–532.
• [3] W. A. Pleskacz, D. Kasprowicz, T. Oleszczak, and W. Kuzmicz, “CMOS standard cells characterization for defect based testing”, in Proc. IEEE Int. Symp. DFT’01, San Francisco, USA, 2001, pp. 384–392.
• [4] W. A. Pleskacz and W. Maly, “Improved yield model for submicron domain”, in Proc. IEEE Int. Symp. DFT’97, Paris, France, 1997, pp. 2–10.
• [5] M. Rakowski, “Szybki ekstraktor obszarow krytycznych na zwarcia w dużych układach VLSI”, Master’s thesis, Warsaw University of Technology, 2006 (in Polish).