Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities

• Autorzy: Głuszko G. , Łukasiak L. , Kilchytska V. , Chung T. M. , Olbrechts B. , Flandrie D. , Raskin J. P.
• Języki publikacji: EN

Abstrakty

EN

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.

Słowa kluczowe

EN

charge-pumping; electrical characterization; interface traps; SOI; water bonding; Si layer transfer

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 3
• Strony: 61--66
• Opis fizyczny: Bibliogr.7 poz., rys., tab.

Twórcy

autor

Głuszko G.

autor

Łukasiak L.

autor

Kilchytska V.

autor

Chung T. M.

autor

Olbrechts B.

autor

Flandrie D.

autor

Raskin J. P.

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology Koszykowa st 75, 00-662 Warsaw, Poland,

Bibliografia

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• [2] T. M. Chung, B. Olbrechts, U. Södervall, S. Bengtsson, D. Flandre, and J.-P. Raskin, “Planar double-gate SOI MOS devices: fabrication by wafer bonding over pre-patterened cavities and electrical characterization”, Solid-State Electron., vol. 51, no. 2, pp. 231–238, 2007.
• [3] S. I. Lai, H. Y. Lin, and C. T. Hu, “Effects of surface treatment on wafer direct bonding process”, Mater. Chem. Phys., vol. 83, pp. 265–272, 2004.
• [4] D. Flandre et al., “Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems”, Solid-State Electron., vol. 45, pp. 541–549, 2001.
• [5] T. Ouisse et al., “Adaptation of the charge pumping technique to gated PIN diodes fabricated on silicon on insulator”, IEEE Trans. Electron Dev., vol. 38, pp. 1432–1444, 1991.
• [6] A. Jakubowski, W. Marciniak, and H. M. Przewłocki, Diagnostic Measurements in LSI/VLSI Integrated Circuits Production. Singapore: World Scientific, 1991.
• [7] M. Bruel, “Silicon on insulator material technology”, Electron. Lett., vol. 31, pp. 1201–1202, 1995.