The influence of annealing (900?C) of ultra-thin PECVD silicon oxynitride layers

• Autorzy: Mroczyński R. , Głuszko G. , Beck R. B. , Jakubowski A. , Ćwil M. , Konarski P. , Hoffman P. , Schmeißer D.
• Języki publikacji: EN

Abstrakty

EN

This work reports on changes in the properties of ultra-thin PECVD silicon oxynitride layers after high- temperature treatment. Possible changes in the structure, composition and electrophysical properties were investigated by means of spectroscopic ellipsometry, XPS, SIMS and electrical characterization methods (C-V, I-V and charge- pumping). The XPS measurements show that SiOxNy is the dominant phase in the ultra-thin layer and high-temperature annealing results in further increase of the oxynitride phase up to 70% of the whole layer. Despite comparable thickness, SIMS measurement indicates a densification of the annealed layer, because sputtering time is increased. It suggests complex changes of physical and chemical properties of the investigated layers taking place during high-temperature annealing. The C-V curves of annealed layers exhibit less frequency dispersion, their leakage and charge-pumping currents are lower when compared to those of as-deposited layers, proving improvement in the gate structure trapping properties due to the annealing process.

Słowa kluczowe

EN

ultra-thin dielectrics; silicon oxynitride; PECVD; CMOS

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 3
• Strony: 16--19
• Opis fizyczny: Bibliogr. 4 poz., rys., tab.

Twórcy

autor

Mroczyński R.

autor

Głuszko G.

autor

Beck R. B.

autor

Jakubowski A.

autor

Ćwil M.

autor

Konarski P.

autor

Hoffman P.

autor

Schmeißer D.

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology Koszykowa st 75, 00-662 Warsaw, Poland,

Bibliografia

• [1] International Technology Roadmap for Semiconductors, http://www.itrs.net/
• [2] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k dielectrics – current status and materials considerations”, J. Appl. Phys., vol. 89, no. 10, pp. 5243–5275, 2001.
• [3] M. L. Green, E. P. Gusev, R. Degraeve, and E. L. Garfunkel, “Ultrathin (< 4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure and physical and electrical limits”, J. Appl. Phys., vol. 90, no. 5, pp. 2057–2121, 2001.
• [4] J. Hee-Hwan et al., “On-chip charge pumping method for characterization of interface states of ultra thin gate oxides in nano-CMOS technology”, in IEDM 2005 Conf., Washington, USA, 2005.