Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data

• Autorzy: Zaunert F. , Endres R. , Stefanov Y. , Schwalke U.
• Języki publikacji: EN

Abstrakty

EN

The evaluation of the world's first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.

Słowa kluczowe

EN

crystalline high-k gate dielectric; rare-earth oxide; praseodymium oxide; gadolinium oxide; damascene metal gate; CMP; CMOS process; TSUPREM4; MEDICI; interface state density; carrier mobility; remote coulomb scattering

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 2
• Strony: 78--85
• Opis fizyczny: Bibliogr. 21 poz., rys.

Twórcy

autor

Zaunert F.

autor

Endres R.

autor

Stefanov Y.

autor

Schwalke U.

• Institute for Semiconductor Technology, Darmstadt University of Technology, Schlossgartenstrassee 8, 64297 Darmstadt, Germany,

Bibliografia

• [1] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide”, in Tech. Dig. IEDM 2000, San Francisco, USA, 2000, pp. 653–656.
• [2] U. Schwalke, “Gate dielectrics: process integration issues and electrical properties”, J. Telecommun. Inform. Technol., no. 1, pp. 7–10, 2005.
• [3] U. Schwalke, K. Boye, K. Haberle, R. Heller, G. Hess, G. Müller, T. Ruland, G. Tzschöckel, J. Osten, A. Fissel, and H.-J. Müssig, “Process integration of crystalline Pr2O3 high-k gate dielectrics”, in Proc. 32nd Eur. Solid State Dev. Res. Conf. ESSDERC, Firenze, Italy, 2002, p. 407.
• [4] H. D. B. Gottlob, M. C. Lemme, T. Mollenhauer, T. Wahlbrink, J. K. Efavi, H. Kurz, Y. Stefanov, K. Haberle, R. Komaragiri, T. Ruland, F. Zaunert, and U. Schwalke, “Introduction of crystalline high-k gate dielectrics in a CMOS process”, in Proc. SiO2, Adv. Dielectr. Rel. Dev., Chamonix Mont-Blanc, France, 2004.
• [5] U. Schwalke, Y. Stefanov, R. Komaragiri, and T. Ruland, “Electrical characterisation of crystalline praseodymium oxide high-k gate dielectric MOSFETs”, in Proc. 33rd Eur. Solid State Dev. Res. Conf. ESSDERC, Estoril, Portugal, 2003, pp. 247–250.
• [6] Y. Stefanov, R. Komaragiri, and U. Schwalke, “Device level and nanoscale electrical characterization of crystalline praseodymium oxide high-k gate dielectric MOSFETs”, in SEMATECH Int. Worksh. Electr. Charact. Reliab. High-k Dev., Austin, USA, 2004.
• [7] Y. Stefanov, G. Hess, G. Tzschöckel, and U. Schwalke, “Global and local charge trapping effects in crystalline praseodymium oxide high-k gate dielectric MOSFETs”, in Electrochem. Soc. Int. Semicond. Technol. Conf. ECS-ISTC, Shanghai, China, 2004.
• [8] Y. Stefanov et al., “Nanoscale electrical characterization of crystalline praseodymium oxide high-k gate dielectric MOSFETs with conductive atomic force microscopy”, in Proc. Seeing Nanosc. III, Santa Barbara, USA, 2005.
• [9] R. Komaragiri, F. Zaunert, and U. Schwalke, “Gate engineering for high-k dielectric and ultra-thin gate oxide CMOS technologies”, in Worksh. Semicond. Adv. Fut. Electron. SAFE 2004, Veldhoven, The Netherlands, 2004.
• [10] R. Endres, Y. Stefanov, and U. Schwalke, “Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology”, in Worksh. Dielectr. Microelectron. WoDiM, Catania, Italy, 2006.
• [11] H. D. B. Gottlob, T. Echtermeyer, T. Mollenhauer, M. Schmidt, J. Efavi, T. Wahlbrink, M. C. Lemme, H. Kurz, R. Endres, Y. Stefanov, U. Schwalke, M. Czernohorsky, E. Bugiel, A. Fissel, and H. J. Osten, “Approaches to CMOS integration of epitaxial gadolinium oxide high-k dielectrics”, in Eur. Solid State Dev. Res. Conf. ESSDERC, Montreux, Switzerland, 2006.
• [12] M. Cassé, L. Thevenod, B. Guillaumot, L. Tosti, F. Martin, J. Mitard, O. Weber, F. Andrieu, T. Ernst, G. Reimbold, T. Billon, M. Mouis, and F. Boulanger, “Carrier transport in HfO2/metal gate MOSFETs: physical insight into critical parameters”, IEEE Trans. Electron Dev., vol. 53, no. 4, pp. 759–768, 2006.
• [13] U. Schwalke, M. Kerber, K. Koller, and H. Jacobs, “EXTIGATE: the ultimate process architecture for submicron CMOS technologies”, IEEE Trans. Electron Dev., vol. 44, no. 11, pp. 2070–2077, 1997.
• [14] Goodfellow Corporation, Material Index, www.goodfellow.com
• [15] P. M. D. Chow and K. L. Wang, “A new ac technique for accurate determination of channel charge and mobility in very thin gate MOSFET’s”, IEEE Trans. Electron Dev., vol. ED-33, pp. 1299–1304, 1986.
• [16] C. L. Huang and G. S. Gildenblat, “Correction factor in the split C-V method for mobility measurements“, Solid-State Electron., vol. 36, pp. 611–615, 1993.
• [17] C. L. Huang, J. V. Faricelli, and N. D. Arora, “A new technique for measuring MOSFET inversion layer mobility”, IEEE Trans. Electron Dev., vol. 40, pp. 1134–1139, 1993.
• [18] D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically related to doping and field”, Proc. IEEE, vol. 55, pp. 2192–2193, 1967.
• [19] S. Selberherr, “Process and device modeling for VLSI”, Microelectron. Reliab., vol. 24, no. 2, pp. 225–257, 1984.
• [20] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
• [21] H. J. Osten, private communication.