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On-wafer wideband characterization: a powerful tool for improving the IC technologies

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage - SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.
Rocznik
Tom
Strony
69--77
Opis fizyczny
Bibliogr. 18 poz., rys.
Twórcy
autor
autor
  • Microwave Laboratory, Université catholique de Louvain (UCL), Place du Levant, 3 B-1348 Louvain-la-Neuve, Belgium, dimitri.lederer@tyndall.ie
Bibliografia
  • [1] P. Su, S. K. H. Fung, W. Liu, and C. Hu, “Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD”, in Proc. Int. Symp. Qual. Electron. Des., San Jose, USA, 2002, pp. 75–76.
  • [2] R. V. Joshi, C. T. Chuang, S. K. H. Fung, F. Assaderaghi, M. Sherony, I. Yang, and G. Shahidi, “Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM”, in Proc. VLSI Tech. Dig., Kyoto, Japan, 2001, pp. 75–76.
  • [3] J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. E. Raynaud, A. Roveda, and H. Brut, “New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides”, in Proc. ESSDERC, Florence, Italy, 2002, pp. 515–518.
  • [4] A. Mercha, J. M. Rafi, E. Simoen, E. Augendre, and C. Claeys, “Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs”, IEEE Trans. Electron Dev., vol. 50, no. 7, pp. 1675–1682, 2003.
  • [5] D. Lederer, D. Flandre, and J.-P. Raskin, “AC behavior gate transconductance for ultra thin gate oxide PD SOI MOS”, IEEE Electron Dev. Lett., vol. 25, no. 2, pp. 104–106, 2004.
  • [6] Y.-C. Tseng et al., “AC floating body effects and the resultant analog circuit issues in submicron floating body and body grounded SOI MOSFETs”, IEEE Trans. Electron Dev., vol. 46, no. 8, pp. 1685–1692, 1999.
  • [7] D. Lederer, D. Flandre, and J.-P. Raskin, “High frequency degradation of body-contacted PD SOI MOSFET output conductance”, Semicond. Sci. Technol., no. 20, pp. 469–472, 2005.
  • [8] M. Dehan and J.-P. Raskin, “Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis”, Elsev. Sci., Perg., Solid-State Electron., vol. 49, pp. 67–72, 2005.
  • [9] D. Lederer, O. Rozeau, and J.-P. Raskin, “Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements”, in Proc. IEEE Int. SOI Conf., Honolulu, Hawaii, USA, 2005, pp. 65–66.
  • [10] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge, “Accurate SOI MOSFET charaterisation at microwave frequencies for device performance optimisation and analogue modelling”, IEEE Trans. Electron Dev., vol. ED-45, no. 5, pp. 1017–1025, 1998.
  • [11] BSIMSOI project, http://www-device.eecs.berkeley.edu/ bsimsoi
  • [12] A. Bracale, V. Ferlet-Cavrois, N. F. D. Pasquet, J.-L. Gautier, J.-L. Pelloie, and J. du Port de Poncharra, “A new approach for SOI devices small-signal parameters extraction”, Anal. Integr. Circ. Sig. Proc., vol. 25, no. 2, pp. 157–169, 2000.
  • [13] D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer, and J.-P. Raskin, “FinFET analog characterization from DC to 110 GHz”, Elsev. Sci. Perg. Solid-State Electron., vol. 49, pp. 1488–1496, 2005.
  • [14] D. Lederer, B. Parvais, A. Mercha, N. Collaert, M. Jurczak, J.-P. Raskin, and S. Decoutere, “Dependence of FinFET RF performance on fin width”, in Proc. 6th Top. Meet. Silic. Monol. Integr. Circ. RF Syst., San Diego, USA, 2006, pp. 8–11.
  • [15] T. M. Chung, B. Olbrechts, D. Flandre, U. Södervall, S. Bengtsson, and J.-P. Raskin, “Planar double-gate SOI MOS devices by wafer bonding over pre-patterned cavities”, in Proc. EUROSOI Worksh., Grenoble, France, 2006, pp. 111–112.
  • [16] G. Pailloncy and J.-P. Raskin, “New de-embedding technique based on Cold-FET measurement”, in 36th Eur. Microw. Week (36th EuMW) Eur. Microw. Conf. (EuMC), Manchester, UK, 2006.
  • [17] R. Anholt and S. Swirhum, “Measurement and analysis of GaAs MESFET parasitic capacitances”, IEEE Trans. Microw. Theory Techn., vol. 39, no. 7, pp. 1247–1251, 1991.
  • [18] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit”, IEEE Trans. Microw. Theory Techn., vol. MTT-36, no. 7, pp. 1151–1159, 1988.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BAT8-0008-0013
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