Challenges for 10 nm MOSFET process integration

• Autorzy: Östling M. , Malm B. G. , Haartman M. , Hallstedt J. , Zhang Z. , Hellström P. E. , Zhang S.
• Języki publikacji: EN

Abstrakty

EN

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

Słowa kluczowe

EN

sstrained silicon; silicon-germanium; silicon-on-insulator (SOI); high-k dielectrics; hafnium oxide; nanowire; low frequency noise; mobility; metal gate

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 2
• Strony: 25--32
• Opis fizyczny: Bibliogr. 34 poz., rys.

Twórcy

autor

Östling M.

autor

Malm B. G.

autor

Haartman M.

autor

Hallstedt J.

autor

Zhang Z.

autor

Hellström P. E.

autor

Zhang S.

• School of Information Technology, KTH - Royal Institute of Technology, P.O. Box 229 164 40 Kista, Sweden,

Bibliografia

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