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State-of-the-art SOI transistors require a very small body. This paper examines the effects of body thinning and thin-gate oxide in SOI MOSFETs on their electrical characteristics. In particular, the influence of film thickness on the interface coupling and carrier mobility is discussed. Due to coupling, the separation between the front and back channels is difficult in ultra-thin SOI MOSFETs. The implementation of the front-gate split C-V method and its limitations for determining the front- and back-channel mobility are described. The mobility in the front channel is smaller than that in the back channel due to additional Coulomb scattering. We also discuss the 3D coupling effects that occur in FinFETs with triple-gate and omega-gate configurations. In low-doped or tall fins the corner effect is suppressed. Narrow devices are virtually immune to substrate effects due to a strong lateral coupling between the two lateral sides of the gate. Short-channel effects are drastically reduced when the lateral coupling screens the drain influence.
Rocznik
Tom
Strony
14--24
Opis fizyczny
Bibliogr. 27 poz., rys.
Twórcy
autor
autor
autor
autor
- IMEP Minatec-INPG, 3 Parvis Louis Néel, Grenoble BP257, France, ohata@enserg.fr
Bibliografia
- [1] D. Hisamoto et al., “A folded-channel MOSFET for deep-sub-tenth micron era”, in IEDM’98 Tech. Dig., San Francisco, USA, 1998, pp. 1032–1034.
- [2] B. Doyle et al., “Tri-gate fully-depleted CMOS transistors: fabrication, design and layout”, in VLSI 2003 Tech. Dig., Washington, USA, 2003, pp. 132–133.
- [3] J.-T. Park, J.-P. Colinge, and C. H. Diaz, “Pi-gate SOI MOSFET”, IEEE Electron Dev. Lett., vol. 22, no. 5, pp. 405–406, 2001.
- [4] F.-L. Yang et al., “25 nm CMOS omega FETs”, in IEDM’02 Tech. Dig., San Francisco, USA, 2002, pp. 255–258.
- [5] C. Jahan et al., “10 nm WFETs transistors with TiN metal gate and HfO2”, in VLSI 2005 Tech. Dig., Kyoto, Japan, 2005, pp. 112–113.
- [6] S. Cristoloveanu and S. S. Li, Electrical Characterization of SOI Materials and Devices. Boston: Kluwer, 1995.
- [7] H.K. Lim and J. G. Fossum, “Threshold voltage of thin-film siliconon- insulator (SOI) MOSFET’s”, IEEE Trans. Electron Dev., vol. 30, no. 10, pp. 1244–1251, 1983.
- [8] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon on insulator transistor with volume inversion: a new device with greatly enhanced performance”, IEEE Electron Dev. Lett., vol. 8, no. 9, pp. 410–412, 1987.
- [9] T. Ouisse, S. Cristoloveanu, and G. Borel, “Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFETs”, Solid-State Electron., vol. 35, no. 2, pp. 142–149, 1992.
- [10] A. Ohata, S. Cristoloveanu, M. Cassé, A. Vandooren, and F. Daugé, “Coupling effect between the front and back interfaces in thin SOI MOSFETs”, Microelectron. Eng., vol. 80, no. 17, pp. 245–248, 2005.
- [11] A. Ohata, J. Pretet, S. Cristoloveanu, and A. Zaslavsky, “Correct biasing rules for virtual DG mode operation in SOI-MOSFETs”, IEEE Trans. Electron Dev., vol. 52, no. 1, pp. 124–125, 2005.
- [12] A. Ohata, S. Cristoloveanu, M. Cassé, A. Vandooren, and F. Daugé, “Characterization of ultra-thin SOI MOSFETs by coupling effect between front and back interfaces”, in IEEE Int. SOI Conf., Hawaii, USA, 2005, pp. 63–64.
- [13] S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata, and G. Ghibaudo, “Ultra-thin fully-depleted SOI MOSFETs: special charge properties and coupling effect”, Solid-State Electron., vol. 51, no. 2, pp. 239–244, 2007.
- [14] A. Ohata, S. Cristoloveanu, and M. Cassé, “Mobility comparison between front and back channels by front-gate split capacitancevoltage method”, Appl. Phys. Lett., vol. 89, no. 3, p. 032104, 2006.
- [15] J. Chen, R. Solomon, T. Y. Chan, K. P. Ko, and C. Hu, “Threshold voltage and CV characteristics of SiO2 MOSFET’s related to Si film thickness variations on SIMOX wafers”, IEEE Trans. Electron Dev., vol. 39, no. 10, pp. 2346–2353, 1992.
- [16] D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, “Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application”, IEEE Trans. Electron Dev., vol. 48, no. 12, pp. 2842–2850, 2001.
- [17] A. Ohata, M. Cassé, and S. Cristoloveanu, “Front and back channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method”, Solid-State Electron., vol. 51, no. 2, pp. 245–251, 2007.
- [18] M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, “SOI MOSFET effective channel mobility”, IEEE Trans. Electron Dev., vol. 41, no. 2, pp. 276–278, 1994.
- [19] J. Choi, Y. Park, and H. Min, “Electron mobility behavior in extremely thin SOI MOSFET’s”, IEEE Electron Dev. Lett., vol. 16, no. 11, pp. 527–529, 1995.
- [20] M. Bawedin, S. Cristoloveanu, J. G. Yun, and D. Flandre, “A New memory effect (MSD) in fully depleted SOI MOSFETs”, Solid-State Electron., vol. 49, no. 9, pp. 1547–1555, 2005.
- [21] M. S. Krishnan, Y. Yeo, Q. Lu, T. King, J. Bokor, and C. Hu, “Remote charge scattering in MOSFETs with ultra-thin gate dielectrics”, in IEDM’98 Tech. Dig., San Francisco, USA, 1998, pp. 571–573.
- [22] J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut, “New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides”, in Proc. 32th Eur. Solid-State Dev. Res. Conf. ESSDERC’02, Firenze, Italy, 2002, pp. 515–518.
- [23] A. Modelli, “Valence band electron tunneling in metal-oxide-siliconstructures”, Appl. Surf. Sci., vol. 30, pp. 298–303, 1987.
- [24] M. Cassé, J. Pretet, S. Cristoloveanu, T. Poiroux, C. Fenouillet- Beranger, F. Fruleux, C. Raynaud, and G. Reimbold, “Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back gate biasing”, Solid-State Electron., vol. 48, no. 7, pp. 1243–1247, 2004.
- [25] K. Akarvardar, S. Cristoloveanu, and P. Gentil, “Threshold voltage model of the SOI 4-gate transistor”, in IEEE Int. SOI Conf., Charleston, USA, 2004, pp. 89–90.
- [26] M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, S. Cristoloveanu, O. Faynot, and C. Jahan, “High tolerance to total ionizing dose of W-shaped gate field-effect transistors”, Appl. Phys. Lett., vol. 88, p. 223511, 2006.
- [27] T. Ernst and S. Cristoloveanu, “Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture”, IEEE Int. SOI Conf., Rohnert Park, USA, 1999, pp. 38–39.
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Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BAT8-0008-0006