SOI nanodevices and materials for CMOS ULSI

• Autorzy: Palestra F.
• Języki publikacji: EN

Abstrakty

EN

A review of recently explored new effects in SOI nanodevices and materials is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAMare also outlined.

Słowa kluczowe

EN

ballistic transport; gate misalignment; GIFBE; mobility enhancement; SOI; strain engineering; tunneling current

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2007
• Tom: nr 2
• Strony: 3--13
• Opis fizyczny: Bibliogr. 32 poz., rys.

Twórcy

autor

Palestra F.

• Institut de Microélectronique, Electromagnétisme et Photonique, IMEP (CNRS-INPG-UJF), INP Grenoble-Minatec, 38016 Grenoble, France,

Bibliografia

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• [25] A. Khakifirooz, O. M. Nayfeh, and D. A Antoniadis, “Assessing the performance limits of ultra-thin double-gate MOSFETs: silicon vs. germanium”, in Proc. IEEE Int. SOI Conf., Charleston, USA, 2004, p. 79.
• [26] C. Yin and P. C. H. Chan, “Characterization and edge direct tunneling leakage of gate misaligned double gate MOSFETs”, in Proc. IEEE Int. SOI Conf., Charleston, USA, 2004, p. 91.
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