Concurrent operation of processors in the bit-byte CPU of a PLC

• Autorzy: Chmiel M. , Hrynkiewicz E.
• Języki publikacji: EN

Abstrakty

EN

The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.

Słowa kluczowe

EN

programmable logic controller; central processing unit; bit-byte structure of CPU; scan time; throughput time; concurrent operation

• Wydawca: Systems Research Institute, Polish Academy of Sciences
• Czasopismo: Control and Cybernetics
• Rocznik: 2010
• Tom: Vol. 39, no 2
• Strony: 559--579
• Opis fizyczny: Bibliogr. 16 poz., rys.

Twórcy

autor

Chmiel M.

autor

Hrynkiewicz E.

• Institute of Electronics, Silesian University of Technology, Akademicka 16, 44-100 Gliwice, Poland,

Bibliografia

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