Powiadomienia systemowe
- Sesja wygasła!
Identyfikatory
Warianty tytułu
Języki publikacji
Abstrakty
The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.
Czasopismo
Rocznik
Tom
Strony
559--579
Opis fizyczny
Bibliogr. 16 poz., rys.
Twórcy
autor
autor
- Institute of Electronics, Silesian University of Technology, Akademicka 16, 44-100 Gliwice, Poland, Miroslaw.Chmiel@polsl.pl
Bibliografia
- ARAMAKI, N., SHIMOKAWA, Y., KUNO, S., SAITOH, T. and HASHIMOTO, H. (1997) A new Architecture for High-performance Programmable Logic Controller. Proceedings of the IECON’97 23rd International Conference on Industrial Electronics. Control and Instrumentation, IEEE 1, New York, USA, 187-190.
- BERGER, H. (2001a) Automating with STEP 7 in LAD and FED - SIMATIC S7-300/400 Programmable Controllers. Siemens AG.
- BERGER, H. (2001b) Automating with STEP 7 in STL and SCL - SIMATIC S7-300/400 Programmable Controllers. Siemens AG.
- CHMIEL, M. (2004) Improvement of Data Exchange Between the Processors of the Bit-Byte CPU of a PLC. PhD Thesis. Gliwice, Poland.
- CHMIEL, M., CIĄŻYŃSKI, W. and HRYNKIEWICZ, E. (1995) An Overview of Process Data Access and Program Execution Methods Applied in PLCs. PDS’95: International Conference Programmable Devices and Systems. Gliwice, Poland 9-10.11.
- CHMIEL, M., CIĄŻYŃSKI, W. and NOWARA, A. (1995) Timers and Counters Applied in PLCs. PDS’95: International Conference Programmable Devices and Systems. Gliwice, Poland 9-10.11.
- CHMIEL, M. and HRYNKIEWICZ, E. (1999) Parallel Bit-Byte CPU structures of Programmable Logic Controllers. International Workshop on ECMS. Liberec, Czech Republic, 67-71.
- CHMIEL, M. and HRYNKIEWICZ, E. (2001) Remarks on Parallel Bit-Byte CPU structures of Programmable Logic Controllers. International Workshop on DESDes. Przytok, Poland, 147-152.
- CHMIEL, M. and HRYNKIEWICZ, E. (2004) Concurrent Operation of the Processors in Bit-Byte CPU of Industrial PLC. International Conference on PDS. Kraków, Poland, November 18-19, 15-20.
- CHMIEL, M. and HRYNKIEWICZ, E. (2005) Remarks on Parallel Bit-Byte CPU structures of Programmable Logic Controllers. In: M.A. Adamski, A. Karatkevich, M. Węgrzyn, eds., Design of Embedded Control Systems. Section V, Springer Science + Business Media, Inc., 231-242.
- CHMIEL, M., HRYNKIEWICZ, E. and MILIK, A. (2005) Concurrent operation of the processors in Bit-Byte CPU of a PLC. Preprints of the IF AC World Congress. Prague, Czech Republic, July 3-8.
- DONANDT, J. (1989) Improving response time of Programmable Logic Controllers by use of a Boolean coprocessor. In: VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks, IEEE Computer Society Press, Washington, DC, 167-169.
- GAŁKA, P. (1995) Podstawy programowania mikrokontrolerów 8051 (Fundamentals of 8051 microcontroller programming; in Polish). Mikom, Warszawa.
- GETKO, Z. (1983) Programowalne systemy sterowania binarnego PLC (Programmable systems of binary control, PLC; in Polish). Elektronizacja, WKiŁ, Warszawa.
- MICHEL, G. (1990) Programmable Logic Controllers, Architecture and Applications. John Wiley & Sons, West Sussex, England.
- MODICON (1990) Modicon 984 Programmable Controller - System Manual. AEG Modicon.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BAT5-0055-0018