Optimized architectures of CABAC CODEC for IA-32-, DSP-and FPGA-based platforms

• Autorzy: Karwowski D. , Domański M.
• Języki publikacji: EN

Abstrakty

EN

Two optimized architectures of Context-based Adaptive Binary Arithmetic Coding (CABAC) are presented in the paper. These are: the software version of CABAC (dedicated to IA-32 and DSP platforms) and the hardware version of CABAC (dedicated to FPGA and ASIC platforms). The paper presents analysis of implementations for both versions of CABAC. The optimized software as well as the hardware version of CABAC was tested in terms of codec throughput.

Słowa kluczowe

EN

optimized architectures; video compression; Context-based Adaptive Binary Arithmetic Coding

• Wydawca: Instytut Telekomunikacji i Informatyki Uniwersytetu Technologiczno-Przyrodniczego w Bydgoszczy
• Czasopismo: Image Processing & Communications
• Rocznik: 2009
• Tom: Vol. 14, no 2-3
• Strony: 5--12
• Opis fizyczny: Bibliogr. 12 poz., rys., wykr.

Twórcy

autor

Karwowski D.

autor

Domański M.

• Poznań University of Technology, Chair of Multimedia Telecommunications and Microelectronics,

Bibliografia

• [1] ISO/TEC 14496-10, Generic Coding of Audio-Visual Objects, Part 10: Advanced Video Coding, March 2006
• [2] H.264/AVC software coordination site - http://bs.hhi.de/~suehring/ tml
• [3] D. Marpe, H. Schwarz, and T. Wiegand, Context-Based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 620-636, July 2003
• [4] IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std 1364-1995, IEEE, 1995.
• [5] Virtex-5 FPGA Family Datasheet. Xilinx, Inc., San Jose, CA, 2007, http://www.xilinx.com/
• [6] Xilinx ISE 9.2i software manuals, http://www.xilinx.com/
• [7] I. Kuon, and J. Rose, Measuring the Gap Between FPGAs and ASIC, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Vol. 26, No. 2, p. 203, February 2007
• [8] D. Marpe, and T. Wiegand, A highly Ecient Multiplication-Free Binary Arithmetic Coder and Its Application in Video Coding, IEEE International Conference on Image Processing (ICIP’03), Barcelona, Spain, September 2003
• [9] D. Marpe, G. Marten, and H. L. Cycon, A Fast Renormalization Technique for H.264/MPEG4-AVC Arithmetic Coding, 51st Internationales Wissenschaftliches Kolloquium Technische Universitat Ilmenau, September 2006
• [10] x264 Project http://www.videolan.org/developers/x264.html
• [11] Texas Instrument, TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor, www.ti.com, July, 2002
• [12] D. Karwowski, M. Domański, High speed CABAC codecs for DSP- and FPGA-based platforms, In Book: Image Processing & Communications Challenges, Ed. Ryszard S. Choraś and Antoni Zabłudowski, Academy Publishing House EXIT, Warsaw 2009, pp. 161-168