Packet switch architecture with multiple output queueing

• Autorzy: Danilewicz G. , Głąbowski M. , Kabaciński W. , Kleban J.
• Języki publikacji: EN

Abstrakty

EN

In this paper the new packet switch architecture with multiple output queuing (MOQ) is proposed. In this architecture the nonblocking switch fabric, which has the capacity of N _N2 N2, and output buffers arranged into N separate queues for each output, are applied. Each of N queues in one output port stores packets directed to this output only from one input. Both switch fabric and buffers can operate at the same speed as input and output ports. This solution does not need any speedup in the switch fabric as well as arbitration logic for taking decisions which packets from inputs will be transferred to outputs. Two possible switch fabric structures are considered: the centralized structure with the switch fabric located on one or several separate boards, and distributed structure with the switch fabric distributed over line cards. Buffer arrangements as separate queues with independent write pointers or as a memory bank with one pointer are also discussed. The mean cell delay and cell loss probability as performance measures for the proposed switch architecture are evaluated and compared with performance of OQ architecture and VOQ architecture. The hardware complexity of OQ, VOQ and presented MOQ are also compared. We conclude that hardware complexity of proposed switch is very similar to VOQ switch but its performance is comparable to OQ switch.

Słowa kluczowe

EN

high-speed packet switching; output queueing; buffer; switch fabric; switching node; multicast

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2004
• Tom: nr 4
• Strony: 76--83
• Opis fizyczny: Bibliogr. 10 poz., il.

Twórcy

autor

Danilewicz G.

• Institute of Electronics and Telecommunications, Poznań University of Technology Piotrowo st 3A, 60-965 Poznań, Poland

autor

Głąbowski M.

• Institute of Electronics and Telecommunications, Poznań University of Technology Piotrowo st 3A, 60-965 Poznań, Poland

autor

Kabaciński W.

• Institute of Electronics and Telecommunications, Poznań University of Technology Piotrowo st 3A, 60-965 Poznań, Poland

autor

Kleban J.

• Institute of Electronics and Telecommunications, Poznań University of Technology Piotrowo st 3A, 60-965 Poznań, Poland

Bibliografia

• [1] K. Yoshigoe and K. J. Christensen, "An evolution to crossbar switches with virtual ouptut queuing and buffered cross points", IEEE Network, vol. 17, no. 5, pp. 48-56, 2003.
• [2] M. K. Karol, M. Hluchyj, and S. Morgan, "Input versus output queuing on a space-division packet switch", IEEE Trans. Commun., vol. 35, pp. 1347-1356, 1987.
• [3] J. Xie and Ch.-T. Lea, "Speedup and buffer division in input/output queuing ATM switches", IEEE Trans. Commun., vol. 51, no. 7, pp. 1195-1203, 2003.
• [4] Y. Tamir and G. Frazier, "High performance multi-queue buffers for VLSI communications switches", in Proc. Comput. Archit., Honolulu, Hawaii, United States, 1988, pp. 343-354.
• [5] T. Anderson et al., "High-speed switch scheduling for local-area networks", ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319-352, 1993.
• [6] H. J. Chao, C. H. Lam, and E. Oki, Broadband Packet Switching Technologies: A Practical Guide to ATM Switches in IP Routers. New York: Wiley, 2001.
• [7] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, "Achieving 100% throughput in input-queued switches", IEEE Trans. Commun., vol. 47, no. 8, pp. 1260-1267, 1999.
• [8] H. J. Chao, "Saturn: a terabit packet switch using dual round-robin", IEEE Commun. Mag., vol. 38, no. 12, pp. 78-84, 2002.
• [9] E. Oki, R. Rojas-Cessa, and H. J. Chao, "A pipeline-based approach for maximal-sized matching scheduling in input-buffered switches", IEEE Commun. Lett., vol. 5, no. 6, pp. 263-265, 2001.
• [10] B. Kraimeche, "Design and analysis of the stacked-banyan ATM siwtch fabric", Comput. Netw., vol. 32, no. 2, pp. 171-184, 2000.