High-level architecture generation of parallel-pipeline FFT processors for real-time R-dimensional signal processing

• Autorzy: Petrovskij A. , Kachinskij M.
• Konferencja: International Workshop on Systems, Signal and Image Processing (4 ; 1997 ; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

Offered algorithm allows to build the structure of the parallel pipeline FFT processors (PPFFT-processor) computing the vector DFT in real time with the minimum structural complexity at given parameters : speed of input data receipt ; structure of a computing element (arhimetic device) and time of the butterfly operation execution. The considered approach to structural synthesis of the PPFFT-processors for R-dimensional signal processing allows to receive the structure of the processor under given restrictions of a specific problem and is the basis for solving the questions of automated design of PPFFT-processors at a structural level.

Słowa kluczowe

EN

computer architecture; FFT; parallel-pipeline processors; signal processing

PL

budowa komputera; procesory równoległe-potokowe; przetwarzanie sygnałów; transformata Fouriera

• Wydawca: Instytut Telekomunikacji i Informatyki Uniwersytetu Technologiczno-Przyrodniczego w Bydgoszczy
• Czasopismo: Image Processing & Communications
• Rocznik: 1998
• Tom: Vol. 4, no 1-2
• Strony: 9--16
• Opis fizyczny: Bibliogr. 6 poz.,

Twórcy

autor

Petrovskij A.

autor

Kachinskij M.

• Computer Science Department, University of Techology Bialystok, ul. Wiejska 45 A, 15-351 Białystok, Poland,