PRET-ization of uRISC Core

• Autorzy: Košt’ál Martin , Sojka Michal

Identyfikatory

DOI

10.15439/2021F126

• Konferencja: Federated Conference on Computer Science and Information Systems (16 ; 02-05.09.2021 ; online)
• Języki publikacji: EN

Abstrakty

EN

Modern safety-critical embedded systems have to be time-deterministic to guarantee safety. One source of time-nondeterminism are interrupts. This paper shows how to mitigate their influence in the system on a commercially available processor IP (Codasip uRISC) can be modified to exhibit time-determinism in real-time workloads and isolate interrupts. We extend the processor with fine-grained multithreading and isolated interrupt handling to localize time-nondeterminism caused by interrupts. We show a comparison between original and extended processors on a selection of TACleBench benchmarks. For interrupt-driven workloads, ideal interrupt isolation is achieved. The proposed modification can be used on other in-order single-issue processors.

Słowa kluczowe

EN

Java; program testing; regression analysis

PL

język Java; testowanie programu; analiza regresji

• Wydawca: Polskie Towarzystwo Informatyczne
• Czasopismo: Annals of Computer Science and Information Systems
• Rocznik: 2021
• Tom: Vol. 25
• Strony: 495--500
• Opis fizyczny: Bibliogr. 17 poz., tab., wykr., rys.

Twórcy

autor

Košt’ál Martin

• Faculty of Electrical Engineering, Czech Technical University in Prague

autor

Sojka Michal

• Czech Institute of Informatics, Robotics and Cybernetics, Czech Technical University in Prague

Bibliografia

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Uwagi

1. Track 3: Software, System and Service Engineering

2. Session: Joint 41st IEEE Software Engineering Workshop and 8th International Workshop on Cyber-Physical Systems