Design techniques in Carry Select Adder using Parallel prefix adder for improved switching energy

• Autorzy: Sam Shylu , Paul Sam , Jingle Diana Jeba , Paul Mano , Anuradha , Sheba Juliet

Identyfikatory

DOI

10.15199/48.2021.05.27

Warianty tytułu

PL

Techniki projektowania sumatora Carry Select wykorzystujące równoległy prefiksowy dodatek w celu poprawy energii przełączania

• Języki publikacji: EN

Abstrakty

EN

A new architecture of Carry select adder has been proposed with improved switching energy using parallel prefix adder. The conventional Carry select adder is the use of two Ripple Carry Adder (RCA) and a multiplexer. The findings in this work are the replacement of one RCA block by Brent Kung adder and the other RCA block by excess-1 converter. Simulation results show that the proposed Carry select adder is proved to have improved switching energy when compared with the other adders in 45nm CMOS process.

PL

Zaproponowano nową architekturę sumatora Carry Select z ulepszoną energią przełączania przy użyciu równoległego sumatora prefiksów. Konwencjonalny dodatek Carry Select wykorzystuje dwa Ripple Carry Adder (RCA) i multiplekser. Wyniki tej pracy to zastąpienie jednego bloku RCA sumatorem Brenta Kunga, a drugiego bloku RCA konwerterem nadmiaru-1. Wyniki symulacji pokazują, że proponowany sumator Carry Select ma lepszą energię przełączania w porównaniu z innymi układami w procesie 45 nm CMOS.

Słowa kluczowe

EN

brent kung adder; carry generation; carry select adder; generation stage; Parallel prefix adder; Pre processing stage

PL

sumator carry select; RCA; Ripple Carry Adder

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2021
• Tom: R. 97, nr 5
• Strony: 152--155
• Opis fizyczny: Bibliogr. 15 poz., rys., tab.

Twórcy

autor

Sam Shylu

• Karunya Institute of Technology & Sciences, Karunya Nagar, Coimbatore-641114

autor

Paul Sam

• Karunya Institute of Technology & Sciences, Karunya Nagar, Coimbatore-641114

autor

Jingle Diana Jeba

• Christ (Deemed to be University),Bangalore-560029

autor

Paul Mano

• Alliance University,Bangalore-560076

autor

Anuradha

• Karunya Institute of Technology & Sciences,Karunya Nagar,Coimbatore-641114

autor

Sheba Juliet

• Alliance University,Bangalore-560076

Bibliografia

• [1] Golda Hepzibah,C.P. Subha,A Novel Implementation of High Speed Modified Brent Kung Carry Select Adder, International Conference of Intelligent systems and Control, (2016), 1-5.
• [2] Basant Kumar Mohanty, Sujit Kumar Patel ,Area-Delay-Power Efficient Carry-Select Adder, International Journal of Advanced Technology and Innovative Research,10(7) ,(2015), 2348- 2370.
• [3] Basant Kumar Mohanty, Sujit Kumar Patel ,Area-Delay-Power Efficient Carry-Select Adder, IEEE transaction on circuits and systems-II: Express briefs, 61(6),
• [2014]. 4]Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi, A lowcost high-speed self-checking carry select adder with multiplefault detection,Procedia Computer Science,141,(2018), 317- 324.
• [5] Shubham Sarkar, Sujqn Sarkar,Jishan Mehedi,Comparison of Various Adders and their VLSI Implementation, 2018 International Conference on Computer Communication and Informatics (ICCCI -2018).
• [6] Abhishek R Hebbar, Piyush Srivastava, Vinod Kumar Joshi, Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder, 8th International Conference on Advances in Computing and Communication, Procedia Computer Science 143, (2018) ,317–324.
• [7] Pallavi Saxena, Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ,(2005).
• [8] Pappu P. Potdukhe; Vishal D. Jaiswal, Design of High Speed Carry Select Adder Using Brent Kung Adder, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) –(2016).
• [9] Kamera Swathi, M. Venkateshwarlu, Design and Estimation of Delay, Power and Area for Parallel Prefix Adders, International Journal of Scientific Engineering and Technology Research, 4(25)(2015).
• [10] Pakkiraiah Chakali, Madhu Kumar Patnala,Design of High Speed Ladner-Fischer Based Carry Select Adder, International Journal of Soft Computing and Engineering (IJSCE) , 3(1), (2013),173-176.
• [11] Guguloth Sreekanth, V Harish , D Mohammad Elias, Design Of Low Power and Area Efficient Carry Select Adder (CSLA) Using Verilog Language,International Journal of Engineering And Science ,6(5),( 2016),61-66.
• [12] Suhas Shirol, Design and Analysis of Carry Select Adder Using Kogge Stone Adder, International Journal of Innovative Research in Computer and Communication Engineering 5(3), (2017),35-40.
• [13] Mohanraj.M, Nethaji.B, Nithya.S, Nivetha.N, Design of Low Power –delay Consumption Kogge stone Parallel Prefix adder for high speed computing,International Journal of Advanced Information Science and Technology (IJAIST) 3(7), (2014),17- 21.
• [14] Sri Phani Ramya , Nimmy Maria Jose, A Low Power Binary to Excess-1 Code Converter Using GDI Technique, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 4(1), (2015),209-214.
• [15] Vimukth John,D.S.Shylu,S.Radha,P.Sam Paul, Joel,Design of a power efficient Kogge stone adder by exploring new OR gate in 45nm CMOS Process,Circuit World,Vol.46,Issue 4, 257- 269,2019.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).