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An Integrated Analog Demultiplexer for Spatial Multiplexing of Local Elements Scheme Using MOS Transistors

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Warianty tytułu
PL
Scalony multiplekser analogowy CMOS dla techniki Spatial Multiplexing
Języki publikacji
EN
Abstrakty
EN
This paper proposes a CMOS analog demultiplexer for Spatial Multiplexing of Local Elements scheme at baseband level. This technique is a front-end receiver architecture which uses only one RF channel, carrying multiplexed information from multiple antennas into one RF single channel. The described circuit has four channels, in which each channel has a differential switch pair and an OTA for amplification and differential to single-ended signal conversion. The specifications and simulation performance are in close agreement, which validate the proposed compact design.
PL
W artykule zaprezentowano analogowy demultiplekser CMOS do przestrzennego multipleksowania (Spatial multiplexing). Ta technika jest stosowana w odbiornikach używających tylko jeden kanał RF i umożliwia multipleksowanie informacji z wielu anten. Opisany układ ma cztery kanały i każdy z kanałów ma różną parę kluczy.
Rocznik
Strony
115--118
Opis fizyczny
Bibliogr. 22 poz., schem., tab., wykr.
Twórcy
  • Universidade Federal do ABC, Rua Santa Adélia, 166 - CEP 09.210-170, Santo André -SP, Brazil
autor
  • Universidade Federal de São João delRei, Rod.: MG 443, KM 7 - CEP: 36.420-000, Ouro Branco MG, Brazil
autor
  • Universidade Estadual de Campinas, Av. Albert Einstein - 400 - CEP: 13.083-852, Campinas - SP, Brazil
Bibliografia
  • [1] A. A. Abidi, “RF CMOS comes of age,” IEEE Journal of Solid-State Circuits, vol. 39, no. 04, pp. 549–561, April 2004.
  • [2] L. C. Kretly and C. E. Capovilla, “A novel antenna array based on quasi-yagi element for adaptive wireless system applications,” IEEE International Microwave and Optoelectronics Conference, vol. 01, pp. 307–312, September 2003.
  • [3] J. Cheng, Y. Kamiya, and T. Ohira, “Adaptive beamforming of espar antenna using sequential perturbation,” IEEE MTT-S International Microwave Symposium Digest, vol. 01, 2001.
  • [4] S. Ishii, A. Hoshikuki, and R. Kohno, “Space hopping scheme undershort range rician multipath fading environment,” IEEE Vehicular Technology Conference, vol. 01, pp. 99–104, May 2000.
  • [5] J. D. Fredrick, Y. Wang, and T. Itoh, “A smart antenna receiver array using a single rf channel and digital beamforming,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 12, pp. 3052–3058, December 2002.
  • [6] ——, “Smart antennas based on spatial multiplexing of local elements SMILE for mutual coupling reduction,” IEEE Transactions on Antennas and Propagation, vol. 52, no. 1, pp. 106–114, January 2004.
  • [7] K. Shinho and Y. E. Wang, “Two-dimensional planar array for digital beamforming and direction-of-arrival estimations,” IEEE Transactions on Vehicular Technology, vol. 58, no. 07, pp. 3137–3144, July 2009.
  • [8] G. DeLaFuente-Cortes, V. R. Gonzalez-Diaz, J. Hernandez-Sanchez, G. Mino-Aguilar, F. Guerrero-Castellanos, O. G. Felix-Beltran, and E. Moreno-Barnosa, “Design constraints for low distortion OTA’s in on-chip analog front-ends,” International Conference on Electronics, Communications and Computing, pp. 236–239, 2013.
  • [9] S. Summart, C. Thongsopa, and W. Jaikla, “OTA based currentmode sinusoidal quadrature oscillator with non-interactive control,” PRZEGLAD ELEKTROTECHNICZNY (Electrical Review), pp. 14–17, July 2012.
  • [10] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, “Low-voltage super class AB CMOS OTA cells with very high slew rate and power efficiency,” IEEE Journal of Solid-State Circuits, vol. 40, no. 05, pp. 1068–1077, May 2005.
  • [11] P. Sun and P. Liu, “Analysis of parasitic effects in triple-well CMOS SPDT switch,” Electronics Letters, vol. 49, no. 11, November 2013.
  • [12] F. J. Huang and K. K. O, “A 0.5-μm CMOS T/R switch for 900-MHz wireless applications,” IEEE Journal of Solid-State Circuits, vol. 36, no. 03, pp. 486–492, March 2001.
  • [13] K. K. O, X. Li, F. J. Huang, and W. Foley, “Cmos components for 802.11b wireless lan applications,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 103–106, 2002.
  • [14] K. Yamamoto, T. Heima, A. Furukawa, M. Ono, Y. Hashizume, H. Komurasaki, S. Maeda, H. Sato, and N. Kato, “A 2.4-ghz band 1.8-v operation single-chip si-cmos t/r-mmic front-end with a low insertion switch,” IEEE Journal of Solid-State Circuits, vol. 36, no. 08, pp. 1186–1197, August 2001.
  • [15] R. H. Caverly, “Linear and nonlinear characteristics of the silicon CMOS monolithic 50 ohms microwave and RF control element,” IEEE Journal of Solid-State Circuits, vol. 34, no. 01, pp. 2323–3228, January 1999.
  • [16] Y. Tsividis, Operation and Modeling of the MOS Transistors, 2nd ed. McGraw-Hill, 1999.
  • [17] Z. Li and K. K. O, “15-GHz fully integrated NMOS switches in a 0.13μm CMOS process,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp. 2323–3228, November 2005.
  • [18] F. J. Huang and K. K. O, “A 900-mhz t/r switch with 0.8 db insertion loss in a 0.5μm cmos process,” IEEE Custom Integrated Circuits Conference, pp. 341–344, 2000.
  • [19] M. Halgas and M. Tadeusiewicz, “Analysis of CMOS circuits having multiple DC operating points,” PRZEGLAD ELEKTROTECHNICZNY (Electrical Review), pp. 40–42, July 2011.
  • [20] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. John Wiley & Sons, 2002.
  • [21] P. E. Allen and D. R. Holberg, CMOS analog circuit design, 2nd ed. Oxford University Press, 2002.
  • [22] A. Hastings, The Art of Analog Layout. Prentice Hall, 2001.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-ae34b2e4-9474-4e88-a8f3-be318c406941
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