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A Systematic Approach to Determining the Duty Cycle for Regenerative Comparator Used in WSN

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
A low power regenerative comparator is very useful in Successive Approximation Register (SAR) type Analog to Digital Converter (ADC) for a Wireless Sensor Node (WSN). A regenerative type comparator generates output pulses by comparing input with a reference input. This paper deals with control of a power with an adjustable duty cycle. The regenerative comparator with an adjustable duty cycle and a positive feedback of a latch will help in improving accuracy, speed and also in achieving the less power consumption. The optimum value of a duty cycle is determined with metastability timing constraints. The proposed low power regenerative comparator circuit is designed and simulated by using TSMC 180 nm CMOS technology. The comparator consumes power as low as 298.54 nW with a regenerative time 264 ps at 1 V power supply.
Słowa kluczowe
Rocznik
Strony
329--333
Opis fizyczny
Bibliogr. 14 poz., rys., tab., wykr.
Twórcy
  • Sardar Patel Institute of Technology, India
autor
  • St. Francis Institute of Technology, Borivali, India
Bibliografia
  • [1] N.Verma and A. P. Chandrakasan, An ultra low energy 12-bit rateresolution scalable SAR ADC for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol.42, no. 6, pp. 1196-1205, Jun. 2007.
  • [2] V. K. Garg, Wireless communications and Networking, San Francisco, CA:Elsevier, 2008.
  • [3] P. Harpe et al., A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra-low-power wireless sensor networks,” in Proc. IEEE Int. ESSCIRC Conf., Bordeaux, France, 2012, pp. 373-376.
  • [4] J. Zheng and A. Jamalipour, Wireless Sensor Networks: A Networking Perspective, Hoboken, New Jersey: John Wiley Sons, 2009.
  • [5] I. C. Villanueva and A. L. Martin, An ultra low energy 8-bit charge redistribution ADC for wireless sensors,” in Proc. IEEE 7th ICST Conf., Wellington, New Zealand, 2013, pp. 198-202.
  • [6] T. Jiang et al., A single-channel, 1.25-GS/s, 6-bit, 6.08 mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444-2453, Oct. 2012.
  • [7] W. Gu et al., Power efficient SAR ADC with optimized settling technique,” in Proc. IEEE 56th Int. Symp. MWSCAS, Columbus, OH, USA, 2013, pp. 1156-1159.
  • [8] S. Wei et al., A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2669-2680, 2006.
  • [9] C. Liu et al., A 1 V 11 fJ/conversion-step 10-bit 10 MS/s asynchronous SAR ADC in 0.18 m CMOS,” in Proc. IEEE Int. Symp. VLSI Circuits, Honolulu, HI, USA, 2010, pp. 241-242.
  • [10] G. Huang and P. Lin, A 15 fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique,” J. Microelectronics, Elsevier, vol. 43, pp. 941-948, Aug. 2012.
  • [11] E. Salman and E. Friedman, Utilizing interdependent timing constraints to enhance robustness in synchronous circuits,” J. Microelectronics, Elsevier, vol. 43, pp. 119-127, Feb. 2012.
  • [12] D. Zhang, A. Bhide, and A. Alvandpour, A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13 m CMOS for medical implant devices,” IEEE J. Solid-State Circuits, vol.47, no.7, pp. 1585-1593, Nov. 2011.
  • [13] Z. Zhu et al., A 0.6 V 100-KS/s, 8-10 b resolution configurable SAR ADC in 0.18 m CMOS,” J. Analog Integr. Circ. Sig. Process, Springer, vol. 75, pp. 335-342, Mar. 2013.
  • [14] B. Razavi, Design of Analog CMOS Integrated Circuits, New Dehli, India: Tata McGraw-Hill, 2012.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-ac356366-192d-442c-b1fb-718602410d53
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