Many-Valued Gates for Reducing the Chip-Area of Integrated Circuits

• Autorzy: Novikov S.
• Języki publikacji: EN

Abstrakty

EN

In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of digital integrated circuits. The semi-custom integrated circuit K-PLA has the architecture of a Programmable Logic Array of a type AND-OR and includes new K-valued valves MAX, MIN and GATE(A,j). A gate T(2/K) ( T(K/2)) is intended for transformation binary (K-valued ) entrance words into K-valued (binary) output words. The method of the logical synthesis with the use K-PLA, T(2/K) and T(K/2) allows to reduce nearly three times the chip-area, which is essential for placing of the circuit’s realization of the system of partial Boolean functions .

Słowa kluczowe

EN

programmable logic array; logical synthesis; semi-custom integrated circuit; many valued gate; reducing of chip-area

• Wydawca: Wydawnictwo Uniwersytetu Przyrodniczo-Humanistycznego w Siedlcach
• Czasopismo: Studia Informatica : systems and information technology
• Rocznik: 2007
• Tom: Vol. 1(8)
• Strony: 7--17
• Opis fizyczny: Bibliogr. 8 poz., rys.

Twórcy

autor

Novikov S.

• Institute of Computer Science, University of Podlasie, Siedlce, Poland

Bibliografia

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• 6. Pyotr Bibilo, Natalia Kirienko. Block synthesis of combinational circuits in the basis of PL A and library gates. Proceedings of The International Workshop on Discrete-Event System Design. Zielona Góra, Technical University of Zielona Góra, 2001, s. 181-186.
• 7. Sergey Novikov. Method of Logical Synthesis of Integrated Circuits in basis K-PLA. Studia Informatica. Systemy i technologie informacyjne. VOLUME 1/2(7), Siedlce, AP, 2006, s. 247-253.
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