Hardware-aware tiling optimization for multi-core systems

• Autorzy: Adamski D. , Jabłoński G.

Identyfikatory

DOI

10.7494/csci.2017.18.2.145

• Języki publikacji: EN

Abstrakty

EN

This paper presents a proposal for a new tool that improves tiling efficiency for a given hardware architecture. This article also describes the correlation between the changing hardware architecture and methods of software optimization. The first chapter includes a short description of the change in hardware architecture that has occurred over the past ten years. The second chapter provides an overview of the tools that will be used in further research. The subsequent sections contain a description of the proposed hardware-aware tool for optimal tiling.

Słowa kluczowe

EN

LLVM; tiling; data locality; polyhedral model

• Wydawca: Wydawnictwa AGH
• Czasopismo: Computer Science
• Rocznik: 2017
• Tom: Vol. 18 (2)
• Strony: 145--162
• Opis fizyczny: Bibliogr. 20 poz., rys.

Twórcy

autor

Adamski D.

• Lodz University of Technology, Department of Microelectronics and Computer Science

autor

Jabłoński G.

• Lodz University of Technology, Department of Microelectronics and Computer Science

Bibliografia

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