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Experimental quantification of electrostatic damage (ESD) in binary reticle with feature of nanometre scale gaps

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PL
Eksperymentalna ocena ilościowa uszkodzeń elektrostatycznych (ESD) w siatce binarnej z cechą przerw w skali nanometrycznej
Języki publikacji
EN
Abstrakty
EN
A Binary reticle for lithography circuit patterning is extremerly senstive to electrostatic field. Damaged is seen on its feature after a breakdown voltage occurred between the metal lines. The experimental quantification of ESD for Binary reticle is performed by direct discharge to the feature of Critical Dimension (CD) of 80 nm to 160 nm. Its breakdown voltage correlated to CD but lower than international standard recommendations and observed Electric Field-Induced Migration (EFM) damaged at CD of < 110 nm but ESD for CD > 110 nm to 160 nm.
PL
Siatka binarna do wzorcowania obwodów litograficznych jest niezwykle wrażliwa na pole elektrostatyczne. Uszkodzenie jest widoczne na jego cechach po wystąpieniu napięcia przebicia między metalowymi liniami. Eksperymentalne oznaczenie ilościowe ESD dla siatki binarnej jest wykonywane przez bezpośrednie wyładowanie do cechy wymiaru krytycznego (CD) od 80 nm do 160 nm. Jego napięcie przebicia było skorelowane z CD, ale niższe niż zalecenia międzynarodowych standardów i zaobserwowano migrację indukowaną polem elektrycznym (EFM) uszkodzoną przy CD < 110 nm, ale ESD dla CD > 110 nm do 160 nm.
Rocznik
Strony
60--63
Opis fizyczny
Bibliogr. 20 poz., rys., tab.
Bibliografia
  • [1] Q. Wu, Y. Li, Y. Yang, S. Chen, and Y. Zhao, “The Law That Guides The Development of Photolithography Technology and The Methodology in The Design of Photolithographic Process,” China Semicond. Technol. Int. Conf. 2020, CSTIC 2020, pp. 3– 8, 2020.
  • [2] N. Mowell et al., “Criticality of Photo Track Monitoring for Lithography Defect Control,” ASMC (Advanced Semicond. Manuf. Conf. Proc., vol. 2019-May, pp. 2019–2022, 2019.
  • [3] M. A. Chik, A. B. Rahim, A. Z. M. Rejab, K. Ibrahim, and U. Hashim, “Discrete Event Simulation Modeling for Semiconductor Fabrication Operation,” IEEE Int. Conf. Semicond. Electron. Proceedings, ICSE, pp. 325–328, 2014.
  • [4] P. Jiang, M. Yuping, and H. Fang, “Photomask With Electrostatic Discharge Protection,” US20200233298A1, 2020.
  • [5] SEMI E163, “SEMI E163-0212 Guide For The Handling Of Reticles And Other Extremely Electrostatic Sensitive (EES) Items Within Specially Designated Areas,” 2012.
  • [6] G. Rider, “Why SEMI Standard E163 Should be Followed for The Protection of Extremely Electrostatic- Sensitive Semiconductors And Similar Devices During Manufacturing, Packaging And Handling,” Glob. Journals, vol. 20, no. 3, 2020.
  • [7] B. Billancourt and E. Souleillet, “Photomask and Method for Reducing Electrostatic Discharge on The Same itwh An ESD Protection Pattern,” 2005.
  • [8] J. Smallwood, “Can Electrostatic Discharge Sensitive Electronic Devices be Damaged by Electrostatic Fields?,” J. Phys. Conf. Ser., vol. 1322, no. 1, 2019.
  • [9] G. Rider, “Electrostatic Risks to Reticles and Damage Prevention Methodology,” Metrol. Insp. Process Control Microlithogr. XXX, vol. 9778, no. March, p. 97782S, 2016.
  • [10] L. Ledernez, F. Olcaytug, H. Yasuda, and G. Urban, “A Modification of Paschen Law for Argon,” Int. Conf. Phenom. Ioniz. Gases, pp. 0–2, 2009.
  • [11] A. Peschot, C. Poulain, N. Bonifaci, and O. Lesaint, “Electrical breakdown voltage in micro- and submicrometer contact gaps (100nm - 10μm) in air and nitrogen,” Electr. Contacts, Proc. Annu. Holm Conf. Electr. Contacts, vol. 2015-Decem, pp. 280– 286, 2015.
  • [12] A. Mayer, “Numerical Testing of The Fowler–Nordheim Equation for The Electronic Field Emission From A Flat Metal and Proposition for an Improved Equation,” J. Vac. Sci. Technol. B, Nanotechnol. Microelectron. Mater. Process. Meas. Phenom., vol. 28, no. 4, pp. 758–762, 2010.
  • [13] J. A. Montoya, L. Levit, and A. Englisch, “A Study of the Mechanisms for ESD Damage to Reticles,” IEEE Trans. Electron. Packag. Manuf., vol. 24–2, pp. 1–8, 2001.
  • [14] G. C. Rider and T. S. Kalkur, “Experimental Quantification of Reticle Electrostatic Damage Below the Threshold for ESD,” Metrol. Insp. Process Control Microlithogr. XXX, vol. 6922, pp. 69221Y-69221Y–11, 2008.
  • [15] A. J. Wallash and L. Levit, “Electrical Breakdown and ESD Phenomena for Devices With Nanometer-to-micron Gaps,” Reliab. Testing, Charact. MEMS/MOEMS II, vol. 4980, p. 87, 2003.
  • [16] ITRS, “International Technology Roadmap Semiconductors - Factory Integration,” in International Technology Roadmap for Semiconductors 2011, 2011.
  • [17] SEMI E78, “SEMI E78-0912 Guide To Assess And Control Electrostatic Discharge (ESD) And Electrostatic Attraction (ESA) For Equipment,” 2012.
  • [18] SEMI E129, SEMI E129-0912 Guide To Assess And Control Electrostatic Charge In A Semiconductor Manufacturing Facility. SEMI, 2012.
  • [19] H. Razman, A. A. M. Isa, W. A. A. W. Razali, M. K. Suaidi, and M. S. I. M. Zin, “A preliminary study of characterization techniques for reticle ESD threshold voltage measurement,” J. Telecommun. Electron. Comput. Eng., vol. 8, no. 1, pp. 53–57, 2016.
  • [20] J. P. Howard, “Interpolation and Extrapolation,” Comput. Methods Numer. Anal. with R, no. February, pp. 95–132, 2018
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-a7a6dd90-7150-4b02-8773-ca280029b035
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