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Multi-core and single-core raspberry Pi microprocessor’s

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PL
Wielordzeniowe i jednordzeniowe mikroprocesory Raspberry Pi
Języki publikacji
EN
Abstrakty
EN
A multi-core processor is defined as an integrated chip that consists of two or more processors used for system performance enhancement, speed improvement, and multitasking performances. They collaborate to execute instructions faster than the single-core processor. Hence, this paper provides an overview of the evolution of the processor architecture and analysis of the multi-core processor's performance compared to the single-core processor. It highlights the difference in Central Processing Unit speed, memory bandwidth, power consumption, and the thermal effect on the CPU speed during throttling for single-core ARM11 with Broadcom BCM2835 and a quad-core Cortex-A72 with Broadcom BCM2711B0. Experimental results show that Cortex-A72 has a memory bandwidth of 29 times larger than the ARM11. The CPU speed benchmark indicates that Cortex-A72 is significantly faster and responds to the thermal throttling better than the ARM11 processor. However, as Cortex-A72 has more processing power, it has drawn more power than the ARM11 processor.
PL
Procesor wielordzeniowy jest definiowany jako zintegrowany układ składający się z dwóch lub więcej procesorów służących do zwiększania wydajności systemu, zwiększania szybkości i wydajności pracy wielozadaniowej. Współpracują, aby wykonywać instrukcje szybciej niż procesor jednordzeniowy. Dlatego niniejszy artykuł zawiera przegląd ewolucji architektury procesora i analizę wydajności procesora wielordzeniowego w porównaniu z procesorem jednordzeniowym. Pokazuje różnicę w szybkości jednostki centralnej, przepustowości pamięci, zużyciu energii i wpływie temperatury na szybkość procesora podczas ograniczania przepustowości dla jednordzeniowego ARM11 z Broadcom BCM2835 i czterordzeniowego Cortex-A72 z Broadcom BCM2711B0. Wyniki eksperymentów pokazują, że Cortex-A72 ma przepustowość pamięci 29 razy większą niż ARM11. Test porównawczy szybkości procesora wskazuje, że Cortex-A72 jest znacznie szybszy i lepiej reaguje na dławienie termiczne niż procesor ARM11. Ponieważ jednak Cortex-A72 ma większą moc obliczeniową, pobrał więcej energii niż procesor ARM11.
Rocznik
Strony
38--43
Opis fizyczny
Bibliogr. 27 poz., rys.
Twórcy
  • Centre for Telecommunication Research and Innovation (CeTRI), Fakulti Kejuruteraan Elektronik dan Kejuruteraan Komputer, Universiti Teknikal Malaysia Melaka
  • Centre for Telecommunication Research and Innovation (CeTRI), Fakulti Kejuruteraan Elektronik dan Kejuruteraan Komputer, Universiti Teknikal Malaysia Melaka
  • Balai Bomba dan Penyelamat Melaka Tengah, Melaka, Malaysia
Bibliografia
  • [1] Wang, L., Tao, J., von Laszewski, G. and Marten, H, Multicores in Cloud Computing: Research Challenges for Applications. JCP, vol. 5, no. 6, pp. 958-964, 2010.
  • [2] Valerievich, Bakulev Aleksandr, Pyurova Tatiana Anatolievna, Bakuleva Marina Alekseevna, Skvortsov Sergei Vladimirovich, Kozlov Maksim Aleksandrovich, and Hrukin Vladimir Ivanovich, “Modern Approaches to the Development Parallel Programs for Modern Multicore Processors,” in 6th Mediterranean conference on embedded computing (MECO) on IEEE, 2017, pp. 1-4.
  • [3] Manumachu, R.R. and Lastovetsky, A, “Bi-Objective Optimization of Data-Parallel Applications on Homogeneous Multicore Clusters for Performance and Energy,” IEEE Transactions on Computers, 2017, vol. 67, no. 2, pp. 160-177.
  • [4] Liu, L. and Qi, D, “An Independent Task Scheduling Algorithm In Heterogeneous Multi-Core Processor Environment,” IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, pp. 142-146, 2018.
  • [5] Rupanetti, D. and Salamy, H. “Task Allocation, Migration and Scheduling for Energy-Efficient Real-Time Multiprocessor Architectures,” Journal of Systems Architecture, vol. 98, pp. 17-26, 2019.
  • [6] Rinku, Dhruva R., and M. Asha Rani, “Analysis of Multi-Threading Time Metric on Single and Multi-Core Cpus with Matrix Multiplication,” in Third International Conference on Advances in Electrical, Electronics, Information, Communication, and Bio-Informatics, pp. 152-155, 2017.
  • [7] Rakhee Chhibber and R.B.Garg, “Multicore Processor, Parallelism and Their Performance Analysis,” International Journal of Advanced Research in Computer Science & Technology, pp.112-121,2009.
  • [8] De Pestel, S., Van den Steen, S., Akram, S. and Eeckhout, L, “RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware,” IEEE Computer Architecture Letters, vol. 17, no. 2, pp. 183-186, 2018.
  • [9] Liao, S.L., Liu, B.X., Cheng, C.T., Li, Z.F. and Wu, X.Y,” Long-Term Generation Scheduling of Hydropower System using Multi-Core Parallelization of Particle Swarm Optimization,” Water Resources Management, vol. 31, no. 9, pp. 2791-2807, 2017.
  • [10] Tyagi, S.K.S., Jain, D.K., Fernandes, S.L. and Muhuri, P.K, “Thermal-Aware Power-Efficient Deadline Based Task Allocation in Multi-Core Processor,” Journal of Computational Science, vol. 19, pp. 112-120.
  • [11] Sethi, A. and Kushwah, “Multicore Processor Technology-Advantages and Challenges,” International Journal of Research in Engineering and Technology, vol. 4, no. pp. 87-89, 2015.
  • [12] Juyal, C., Kulkarni, S., Kumari, S., Peri, S. and Somani, A, “Achieving Starvation-Freedom with Greater Concurrency in Multi-Version Object-based Transactional Memory Systems,” In International Symposium on Stabilizing, Safety, and Security of Distributed Systems. Springer, pp. 209-227. 2019.
  • [13] Hassan, M., Kaushik, A.M. and Patel, “Predictable Cache Coherence for Multi-Core Real-Time Systems,” in IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 235-246, 2017.
  • [14] Gonzalez, C., Floyd, M., Fluhr, E., Restle, P., Dreps, D.,Sperling, M., Rao, R., Hogenmiller, D., Vezyrtis, C., Chuang, P. and Lewis, D., “The 24-Core POWER9 Processor with Adaptive Clocking, 25-Gb/S Accelerator Links and 16-Gb/S Pcie Gen4,” IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 91-101, 2017.
  • [15] Zeebaree, S.R., Haji, L.M., Rashid, I., Zebari, R.R., Ahmed, O.M., Jacksi, K. and Shukur, H.M., “Multicomputer Multicore System Influence on Maximum Multi-Processes Execution Time,” TEST Engineering & Management, vol. 83, no. 3, pp. 14921-14931, 2020.
  • [16] Manda, V.B., Kushal, V. and Ramasubramanian, N, “An Elegant Home Automation System Using GSM and ARM-Based Architecture,” IEEE Potentials, vol. 37 no. 5, pp. 43-48, 2018.
  • [17] Chen, C., Xiang, X., Liu, C., Shang, Y., Guo, R., Liu, D., Lu, Y., Hao, Z., Luo, J., Chen, Z. and Li, C, “A Commercial Multi-Core 12-Stage Pipeline Out-Of-Order 64-Bit High Performance RiscV Processor with Vector Extension: Industrial Product,” in 2020ACM/IEEE 47th Annual International Symposium on Computer Architecture, pp. 52-64.
  • [18] Bartók, R. and Vásárhelyi, J. “Parallelization of FIVE Method on Multicore Embedded System,” in 2018 19th International Carpathian Control Conference on IEEE, pp. 400-403, 2018.
  • [19] Bui, J., Xu, C. and Gurumurthi, S. “Understanding Performance Issues on Both Single Core and Multi-Core Architecture,” Computer Organization, pp. 1-8, 2007.
  • [20] Mohanty, R.P., Turuk, A.K. and Sahoo, B. “Analyzing the Performance of Multi-Core Architecture”, 1st Int. Conf. On Computing, Communication and Sensor Network, CCSN-2012.
  • [21] Tyagi, S.K.S., Jain, D.K., Fernandes, S.L. and Muhuri, P.K. 2017. Thermal-Aware Power-Efficient Deadline Based Task Allocation in Multi-Core Processor,” Journal of Computational Science, vol. 19, pp. 112-120, 2012.
  • [22] Xiao, J., Altmeyer, S. and Pimentel, A, “Schedulability Analysis of Non-Preemptive Real-Time Scheduling for Multicore Processors with Shared Caches,” in 2017 IEEE Real-Time Systems Symposium, pp.199-208, 2017.
  • [23] Valery, O., Liu, P. and Wu, J.J, “A Collaborative CPU–GPU Approach for Principal Component Analysis on Mobile Heterogeneous Platforms,” Journal of Parallel and Distributed Computing, vol. 120, pp. 44-61, 2018.
  • [24] Benoit-Cattin, T., Velasco-Montero, D. and Fernández-Berni, J., “Impact of Thermal Throttling on Long-Term Visual Inference in a CPU-Based Edge Device,” Electronics, vol. 9, no. 12, pp. 2106, 2020.
  • [25] N.Sainudin, J.M Sultan, F.Idris and M.Azuani, “Data Collision and Interference Minimization in Wireless Sensor Network using Node Data Addressing with Random Access Time”, Jurnal Kejuruteraan, Vol 33(4), pp.1105-1112, 2021.
  • [26] Raspberry Pi Compute Module 3+ Lite, 9 Raspberry Pi (Trading) Ltd, viewed 16 Mei 2021,URL:https://www.raspberrypi.org/
  • [27] Z.Hamadouche, M.Khiat, A. Chaker, “Nonlinear Controllers Design for Plug-in Hybrid Electric Vehicle”, Prezeglad Elektrotechniczny, vol. 6 ,p. 149, 2022.
Uwagi
Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-a51d5222-5a35-47b2-8fe8-816dffb106b4
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