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Warianty tytułu
Języki publikacji
Abstrakty
This paper presents a cost-effective technique for reducing the delay dispersion of the conventional comparator for level-crossing Analog-to -Digital Converters. Only three transistors, representing a variable driving-current block (VDCB), have been added to the conventional comparator circuit. The VDCB attempts to control the charging behavior of the difference amplifier’ output node. The added block incurs small area overhead and low power consumption compared with the previous works. The proposed circuit has been implemented in MOSIS 130nm technology. The simulation results indicate that the overdrive-related propagation delay dispersion of the proposed technique is reduced to 23% of its counterpart in the conventional comparator. The active area of the proposed circuit is 140.2 μm2 and the power consumption is 227μW at 200MHz. For the sake of scalability check, the proposed circuit is also designed and simulated using 45nm technology. The simulation results came in the same direction, which implies the scalability of the proposed circuit.
Rocznik
Tom
Strony
72--78
Opis fizyczny
Bibliogr. 19 poz.
Twórcy
autor
- Department of Electrical Engineering, College of Engineering, King Saud University, Kingdom of Saudi Arabia and the Department of Electrical Engineering, Faculty of Engineering, Assiut University, Assiut 71516, Egypt
autor
- Department of Electrical Engineering, Faculty of Engineering, Assiut University, Assiut 71516, Egypt
Bibliografia
- [1] N. Sayiner et al, "A Level-Crossing Sampling Scheme for A/D Conversion", IEEE Transaction on Circuits and Systems. Vol. 43, No. 4, April-1996, pp:335 -339.
- [2] E. Allier et al, "A New Class of Asynchronous A/D Converters Based on Time Quantization", Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC'03).
- [3] F. Akopyan et al, "A Level-Crossing Flash Asynchronous Analog-to-Digital Converter", Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), 2006.
- [4] K B. Schell et al, "A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation", IEEE Journal of Solid State Circuits, Vol. 43, No. 11, November-2008, pp: 2472 - 2481.
- [5] T. Wang et al ,"A Level-Crossing Analog-to-Digital Converter With Triangular Dither", IEEE Transaction on Circuits and Systems. Vol. 56, No. 9, September- 2009, pp: 2089 - 2099.
- [6] K. Kozmin et al, "Level -Crossing ADC performance Evaluation Toward Ultrasound Application", IEEE Transaction on Circuits and Systems. Vol. 56, No. 8, August- 2009, Vol. 56, No. 8 September- 2009, pp: 1708 - 1719.
- [7] Minjae Lee, Asad A. Abidi, "A9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue", IEEE JSSC, VOL. 43, NO. 4, April 2008, pp: 769-777.
- [8] S. Komatsu, T. J. Yamaguchi, M. Abbas, et al, " A CMOS Flash TDC with 2.6 -4.2 ps Resolution Using An Array of Unbalanced Arbiters", IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.3, March 2014, pp777-780.
- [9] Dudek, P.; Szczepanski, S. ; Hatfield, J.V., " A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line", IEEE Journal of Solid-State Circuits, Vol. :35 , No. 2, pp 240-247, Feb. 2000.
- [10] M. Lee and A. A. Abidi, "A 9 b, 1.25 ps resolution coarse–fine time to-digital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol. 43, no. 4, 2008 pp. 769-777.
- [11] Dandan Zhang, Hai-Gang Yang,Wenrui Zhu, Wei Li, Zhihong Huang, Lin Li, and Tianyi Li, " A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 11, NOVEMBER 2015, pp: 2680-2684.
- [12] Ping Lu, YingWu, and Pietro Andreani, "A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 11, NOVEMBER 2016, pp: 1019-1023.
- [13] Jose M. de la Rosa, Richard Schreier, Kong-Pang Pun, and Shanthi Pavan," Next-Generation Delta-Sigma Converters: Trends and Perspectives", IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 4, DECEMBER 2015, pp:484-499.
- [14] Jin Wu, Qi Jiang, Ke Song, Lixia Zheng, Dongchen Sun, and Weifeng Sun," Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 64, NO. 2, FEBRUARY 2017, pp:181-185.
- [15] K Kozmin et al, "A low propagation delay dispersion comparator for a level-crossing AD converter", Analog Integr Circ Sig Process (2010) 62 :51-61.
- [16] S. Naraghi et al, " A 9 bit, 14pW and 0.06 mm2 Pulse Position Modulation ADC in 90nm digital CMOS", ISSCC2009, pp: 168- 169.
- [17] M. Abbas et al "Novel Technique for Minimizing the Comparator Delay Dispersion in 65nm CMOS Technology", IEEE ICECS2011.
- [18] K. Khalil et al, "Novel Technique for Reducing the Comparator Delay Dispersion in 45nm CMOS Technology for Level-Crossing ADCs", ISCDG2012.
- [19] L. Pang et al, "Measurement and Analysis of Variability in 45nm Strained- Si CMOS Technology", IEEE 2008 Custom Integrated Circuits Conference (CICC).
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-a3d653fd-edb5-47fe-aeb4-c653e081dcb1