Metoda reprezentacji pośredniej programu PLC opisanego za pomocą języków LD i SFC na potrzeby syntezy sprzętowej

• Autorzy: Milik A.

Warianty tytułu

EN

A common intermediate representation of LD and SFC programs for hardware synthesis purposes

• Języki publikacji: PL

Abstrakty

PL

W artykule przedstawiono metody reprezentacji pośredniej programu sterowania opisanego językiem LD oraz SFC zgodnie z IEC61131-3, opracowane na potrzeby syntezy sprzętowej kładów sterowania PLC implementowanych w strukturach programowalnych FPGA. W opisie wykorzystano oryginalną implementację grafu skierowanego. Przedstawiono opracowane reguły odwzorowania, zapewniające zachowanie zależności sekwencyjnych przy jednoczesnym uzyskaniu maksymalnego zrównoleglenia działania. Przedstawiono również zarys metod syntezy na podstawie opracowanego odwzorowania pośredniego.

EN

The increased performance of a PLC can be achieved by direct implementation of a control program in an FPGA device [3, 6, 7, 8, 12, 13]. The paper presents a methodology of transforming a standard PLC program given by LD or SFC according to IEC61131-3 to the common intermediate form dedicated for logic synthesis. The intermediate form of the control program is represented by a data flow graph (DFG, Fig. 1). The set of nodes is carefully selected to minimize the number of different types of nodes while assuring implementation of PLC behavior. Attributed edges and multiple argument nodes are used to reduce size of DFG (Fig. 2). The developed method for creating a DAG maintains sequential dependencies between variables and revel operations parallelism. In PLC programs the variables pass values between operations and computation cycles. In order to maintain sequential dependencies, value assignment to a variable is observed. If the accessed variable has not been assigned, its value is used for a driving node (Fig. 3). The SFC is based on step, actions and transitions [2]. The step variable in the DFG is represented by a JK flip-flop equivalent. The activation function of a step is based on analysis of its dependencies with preceding and succeeding steps and transitions (Fig. 5). Actions that are bounded with steps are controlled according to their types (Fig. 6). The presented intermediated representation has been successfully applied to synthesize a PLC implemented in an FPGA device.

Słowa kluczowe

PL

sterownik programowalny; diagram stykowy; LD; sekwencyjny schemat funkcji; SFC; synteza logiczna wysokiego poziomu; graf przepływu danych; DFG; FPGA; układy rekonfigurowane

EN

PLC; FPGA; high level logic synthesis; LD; SFC; DFG (data flow graph); data flow graph; ladder diagram

• Wydawca: Wydawnictwo PAK
• Czasopismo: Pomiary Automatyka Kontrola
• Rocznik: 2013
• Tom: R. 59, nr 8
• Strony: 799--802
• Opis fizyczny: Bibliogr. 13 poz., rys., wzory

Twórcy

autor

Milik A.

• Politechnika Śląska, Instytut Elektroniki, ul. Akademicka 16, 44-100 Gliwice

Bibliografia

• [1] Chmiel M., Hrynkiewicz E.: Concurrent operation of processors in the bit-byte CPU of a PLC. Control Cybernetics. 2010, vol. 39 nr 2, pp. 559-579.
• [2] David R.: Grafcet: A Powerful Tool for Sepcification of Logic Controllers. IEEE Transactions on Control Systems Technology, vol. 3, no. 3, 1995, pp 253-268.
• [3] D. Du, X. Xu, and K. Yamazaki: A study on the generation of silicon based hardware PLC by means of the direct conversion of the ladder diagram to circuit design language. Springer London, 2010, vol. 49.
• [4] Economakos C., Economakos G.: C-based PLC to FPGA translation and implementation: The effects of coding styles, 16th International Conference on System Theory, Control and Computing (ICSTCC), 2012 , pp. 1-6, 12-14 Oct. 2012.
• [5] D. Gajski, N. Dutt, A. We, S. Lin: High-Level Synthesis Introduction to Chip and System Design, Kluwer Academic Publishers, 1994.
• [6] Ichikawa S., Akinaka M., Kieda R., Yamamoto H.: Converting PLC instruction sequence into logic circuit: A preliminary study, IEEE International Symposium on Industrial Electronics, July 2006, vol. 4, pp. 2930-2935.
• [7] Milik A., Hrynkiewicz E.: Synthesis and implementation of reconfigurable PLC. International Journal of Electronics and Telecommunications, vol. 58, nr 1, March 2012, pp. 85-94.
• [8] Mocha J., Kania D.: Metoda sprzętowej realizacji programu LD z wykorzystaniem układów FPGA, Pomiary Autom. Kontrola 2012 vol. 58 nr 1, s. 88-92.
• [9] Philippot A., Tajer A.: From GRAFCET to Equivalent Graph for synthesis control of discrete events systems, 18th Mediterranean Conference on Control & Automation (MED), 2010, pp. 683-688.
• [10] Subbaraman S., Patil, M. M., Nilkund, P. S.: Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code, 11th International Conference on Control Automation Robotics & Vision (ICARCV), pp. 1791-1795, 7-10 Dec. 2010.
• [11] Wirth N.: Algorytmy + Struktury Danych = Programy” WNT, Warszawa 1989.
• [12] Yadong L., Kazuo Y., Makoto F., Masahiko M.: Model-driven programmable logic controller design and FPGA-based hardware implementation, ASME International Design Engineering Technical Conferences and Computers and Information in Engineering Conference-DETC2005, 2005, pp. 81-88.
• [13] Welch J. T.; Carletta J.: A direct mapping FPGA architecture for industrial process control applications, International Conference on Computer Design, 2000, pp. 595-598, 2000.