PSO based optimal location and sizing of SVC for novel multiobjective voltage stability analysis during N – 2 line contingency

• Autorzy: Mangaiyarkarasi S. P , Sree Renga Raja T.

Identyfikatory

DOI

10.2478/aee-2014-0037

• Języki publikacji: EN

Abstrakty

EN

In this paper voltage stability is analysed based not only on the voltage deviations from the nominal values but also on the number of limit violating buses and severity of voltage limit violations. The expression of the actual state of the system as a numerical index like severity, aids the system operator in taking better security related decisions at control centres both during a period of contingency and also at a highly stressed operating condition. In contrary to conventional N – 1 contingency analysis, Northern Electric Reliability Council (NERC) recommends N – 2 line contingency analysis. The decision of the system operator to overcome the present contingency state of the system must blend harmoniously with the stability of the system. Hence the work presents a novel N – 2 contingency analysis based on the continuous severity function of the system. The study is performed on 4005 possible combinations of N – 2 contingency states for the practical Indian Utility 62 bus system. Static VAr Compensator is used to improve voltage profile during line contingencies. A multi- objective optimization with the objective of minimizing the voltage deviation and also the number of limit violating bus with optimal location and optimal sizing of SVC is achieved by Particle Swarm Optimization algorithm.

Słowa kluczowe

EN

N – 2 contingency analysis; voltage severity; particle swarm optimization (PSO); SVC; power system planning

• Wydawca: Polish Academy of Sciences, Committee on Electrical Engineering
• Czasopismo: Archives of Electrical Engineering
• Rocznik: 2014
• Tom: Vol. 63, nr 4
• Strony: 535--550
• Opis fizyczny: Bibliogr. 32 poz., wykr., wz.

Twórcy

autor

Mangaiyarkarasi S. P

• Department of Electrical and Electronics Engineering Anna University – BIT Campus, Trichy Tiruchirappalli, Tamilnadu, India 620024

autor

Sree Renga Raja T.

• Department of Electrical and Electronics Engineering Anna University – BIT Campus, Trichy Tiruchirappalli, Tamilnadu, India 620024

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