Optimized Inter Prediction for H.264 Video Codec

• Autorzy: Bernatin T. , Sundari G. , Anselin Nisha Sahaya , Godwin Premi M. S.

Identyfikatory

DOI

10.24425/ijet.2021.135981

• Języki publikacji: EN

Abstrakty

EN

High definition video transmission is one of the prime demands of modern day communication. Changing needs demand diverse features to be offered by the video codec standards, H.264 fits to these requirements for video compression. In this work, an attempt has been made to optimize the inter prediction along with improved intra prediction to ensure the minimal bit rates thereby reduction in the channel bandwidth, which is required in most of the wireless applications. In intraprediction, only DC prediction mode is chosen out of 9 modes with 4*4 luma blocks that reduces the coding complexity towards optimal logic utilization in order to support typical FPGA board for hardware implementation. Most significantly, Inter prediction is carried out utilizing the M9K blocks efficiently with proper timing synchronization to reduce the latency in the encoding operation. Experimental set up comprising of two Altera DE2-115 boards connected through Ethernet cable demonstrated the video transmission. These optimized intra prediction and inter prediction stages resulted in significant improvement in the video compression possessing good subjective quality and increased video compression.

Słowa kluczowe

EN

H.264; intra prediction; inter prediction; M9K; timing synchronization; QP

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2021
• Tom: Vol. 67, No. 2
• Strony: 309--314
• Opis fizyczny: Bibliogr. 6 poz., fot., schem., tab.

Twórcy

autor

Bernatin T.

• Sathyabama Institute of Science and Technology, India

autor

Sundari G.

• Sathyabama Institute of Science and Technology, India

autor

Anselin Nisha Sahaya

• Sathyabama Institute of Science and Technology, India

autor

Godwin Premi M. S.

• Sathyabama Institute of Science and Technology, India

Bibliografia

• [1] Bernatin, T., Sundari, G., “ Video compression based on Hybrid transform and quantization with Huffman coding for video codec”, International conference on control, instrumentation, communication and computational technologies (ICCICCT), pp 476-480, IEEE.
• [2] The Evolution of H.264 From Codec to System Architecture, White Paper, VBrick Systems, December, 2010
• [3] Arun Kumar Pradhan, Lalit Kumar Kanoje and BiswaRanjan Swain, 2013 “FPGA based High Performance CAVLC Implementation for H.264 Video Coding” International Journal of Computer Applications (0975 – 8887) Volume 69 – No. 10.
• [4] Teng Wang, Chih-Kuang Chen, Qi-Hua Yang and Xin-An Wang (2012), “FPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications”, Advances in CSIE, Springer-Verlag Berlin Heidelberg, Vol. 2, AISC 169, pp. 345-352
• [5] Gwo-Long Li et al. (2013), “135-MHz258-K gates VLSI design for all-intra H.264/AVC scalable video encoder”, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., Vol. 21, No. 4, pp. 636-647
• [6] Kuo, H.-C., Wu, L.-C., Huang, H.-T., Hsu, S.-T. and Lin, Y.-L. (2013), “A low power high-performance H.264/AVC intra-frame encoder for 1080pHD video”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 19, No. 6, pp. 925-938

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).