A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks

• Autorzy: Kavitha S. , Hashim Fazida Hanim , Kamal Noorfazila

Identyfikatory

DOI

10.24425/ijet.2019.126316

• Języki publikacji: EN

Abstrakty

EN

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

Słowa kluczowe

EN

EDAC; ALU; speed; block reduction; power; slew rate

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2019
• Tom: Vol. 65, No. 2
• Strony: 313--318
• Opis fizyczny: Bibliogr. 15 poz., tab., rys.

Twórcy

autor

Kavitha S.

• Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia

autor

Hashim Fazida Hanim

• Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia

autor

Kamal Noorfazila

• Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia

Bibliografia

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Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).