Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

• Autorzy: Śniatała P. , Naumowicz M. , Handkiewicz A. , Szczęsny S. , Melo J. L. A. , Paulino N. , Goes J.

Identyfikatory

DOI

10.1515/bpasts-2015-0104

• Języki publikacji: EN

Abstrakty

EN

The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

Słowa kluczowe

EN

sigma-delta; current comparator; CAE

PL

sigma-delta; komparator; CAE

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2015
• Tom: Vol. 63, nr 4
• Strony: 919--922
• Opis fizyczny: Bibliogr. 13 poz., rys., tab., wykr.

Twórcy

autor

Śniatała P.

• Poznań University of Technology, 3A Piotorowo St., 60-965 Poznań, Poland

autor

Naumowicz M.

• Poznań University of Technology, 3A Piotorowo St., 60-965 Poznań, Poland

autor

Handkiewicz A.

• Poznań University of Technology, 3A Piotorowo St., 60-965 Poznań, Poland

autor

Szczęsny S.

• Poznań University of Technology, 3A Piotorowo St., 60-965 Poznań, Poland

autor

Melo J. L. A.

• Poznań University of Technology, 3A Piotorowo St., 60-965 Poznań, Poland

autor

Paulino N.

• UNINOVA/CTS, Universidade Nova de Lisboa, 2829-516 Caparica, Portugal

autor

Goes J.

• UNINOVA/CTS, Universidade Nova de Lisboa, 2829-516 Caparica, Portugal

Bibliografia

• [1] R. Suszyński and K. Wawryn, “Rapid prototyping of algorithmic A/D converters based on FPAA devices”, Bull. Pol. Ac.: Tech. 61 (3), 691-696 (2013).
• [2] K. Wawryn and R. Suszyński, “Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system”, Bull. Pol. Ac.: Tech. 61 (4), 979-988 (2013).
• [3] J.R. Custodio, J. Goes, N. Paulino, J.P. Oliveira, and E. Bruun, “A 1.2-V 165-/spl mu/W 0.29-mm2 multibit sigma-delta ADC for hearing aids using nonlinear DACs and with over 91 dB dynamic-range”, Biomedical Circuits and Systems, IEEE Trans. 7 (3), 376-385 (2013).
• [4] J. Nakamura, B. Pain, T. Nomoto, T. Nakamura, and E.R. Fossum, “On-focal-plane signal processing for current-mode active pixel sensors”, IEEE Trans. Electron Devices 44, 1747-1758 (1997).
• [5] S.L. Smith and E. Sanchez-Sinencio, “Low voltage integrators for high-frequency CMOS filters using current mode techniques”, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing 43, 39-48 (1996).
• [6] R. Zele and D. Allstot, “Low-power cmos continuous-time filters”, IEEE J. Solid-State Circuits 31, 157-158 (1996).
• [7] D. Freitas and K. Current, “CMOS current comparator circuit”, Electronics Letters 17, 695-697 (1983).
• [8] H. Träff, “Novel approach to high speed CMOS current comparators”, Electronics Letters 28, 310-312 (1992).
• [9] M. Naumowicz, M. Melosik, P. Katarzynski, and A. Handkiewicz, “Automation of CMOS technology migration illustrated by RGB to YCrCb”, Opto-Electro. Rev. 21, 326-331 (2013).
• [10] R. Hooke and T. Jeeves, “Direct search solutions of numerical and statistical problems”, J. Association for Computing Machinery 8, 212-229 (1961).
• [11] Y. Aiba, K. Tomioka, Y. Nakashima, K. Hamashita, and B.-S. Song, “A fifth-order G m-C continuous-time ΔΣ modulator with process-insensitive input linear range”, Solid-State Circuits, IEEE J. 44, 2381-2391 (2009).
• [12] T. Song, Z. Cao, and S. Yan, “A 2.7-mW 2-MHz continuoustime ΔΣ modulator with a hybrid active-passive loop filter”, IEEE J. Solid-State Circuits 43, 330-341 (2008).
• [13] J.L.A. de Melo, “A low power 1-MHz continuous-time ΔΣ M using a passive loop filter designed with a genetic algorithm tool”, Proc. IEEE Int. Symp. Circuits Systems ISCAS’13, 586-589 (2013).