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CHB inverter with DC-link capacitor balancing and total harmonic minimization

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Języki publikacji
EN
Abstrakty
EN
A cascaded H-bridge (CHB) multilevel inverter generally requires several DC sources. An alternative option is to replace the separate DC source feeding an H-bridge cell with a capacitor, while maintaining the other H-bridge cell with a real DC voltage source. In this paper a 7-level cascaded H-bridge inverter with a single DC-source is presented. This paper focuses mainly to achieve effective capacitor voltage balancing and selective harmonic elimination (SHE) based on the Newton Raphson algorithm (N–R). It shows hope to reduce the voltage ripple of the capacitors, which leads to higher power conversion efficiency with equal power distribution, reduces the initial cost, and complexity hence it is apt for industrial applications. Simulation results support the proposed control technique.
Rocznik
Strony
81--93
Opis fizyczny
Bibliogr. 25 poz., rys., tab., wz.
Twórcy
autor
  • Laboratory of Robotics, Informatics and Complex Systems (RISC) National Engineering School of Tunis
  • Higher Institute of Information and Communication Technologies University of Carthage
autor
  • Laboratory of Robotics, Informatics and Complex Systems (RISC) National Engineering School of Tunis
  • Higher Institute of Information and Communication Technologies University of Carthage
autor
  • Laboratory of Robotics, Informatics and Complex Systems (RISC) National Engineering School of Tunis
  • Higher Institute of Information and Communication Technologies University of Carthage
Bibliografia
  • [1] Sepahvand H., Liao J., Ferdowsi M., Keith A., Corzine K.A., Capacitor Voltage Balancing in Single-DC-Source Cascaded H-Bridge Multilevel Converters Using Phase Shift Modulation, IEEE transactions on Industrial Electronics, vol. 60, no. 9, September (2013).
  • [2] Stala R., A natural DC-link voltage balancing of diode-clamped inverters in parallel systems, IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 5008–5018 (2013).
  • [3] Kou X., Corzine K.A., Familiant Y.L., A Unique Fault-Tolerant Design for Flying Capacitor Multilevel Inverter, IEEE Transaction on Power Electronics, vol. 19, no. 4, pp. 979–987 (2004).
  • [4] McGrath P., Holmes D.G., KongW.Y., A decentralized controller architecture for a cascaded h-bridge multilevel converter, IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1169–1178 (2014).
  • [5] Kirubakaran A., Vijayakumar D., Development of LabVIEW-based multilevel inverter with reduced number of switches, Int. J. Power Electronics, vol. 6, no. 1, pp. 88–102 (2014).
  • [6] Nagaraja Rao S., Ashok D.V., Sai Babu Ch., New Multilevel Inverter Topology with reduced number of Switches using Advanced Modulation Strategies, International Conference on Power, Energy and Control, Dindigul, India (2013).
  • [7] Malinowski M., Gopakumar K., Rodriguez R., Pérez M.A., A Survey on Cascaded Multilevel Inverters, IEEE Transactions on Industrial Electronics, vol. 57, no. 7 (2010).
  • [8] Cecati C., Ciancetta F., Siano P., A multilevel inverter for photovoltaic systems with fuzzy logic control, IEEE Trans. Ind. Electron., vol. 57, no. 12, pp. 4115–4125 (2010).
  • [9] Dixon J., Pereda J., Castillo C., Bosch S., Asymmetrical multilevel inverter for traction drives using only one dc supply, IEEE Trans. Veh. Technol., vol. 59, no. 8, pp. 3736–3743 (2010).
  • [10] Jingsheng L., Integration of energy storage components with cascaded H-bridge multilevel converters, PhD Thesis, Faculty of the Graduate School of the MISSOURI University of Science and Technology, Rolla, Missouri, United States (2009).
  • [11] Srikanthan S., Mishra M.K., DC capacitor voltage equalization in neutral clamped inverters for DSTATCOM application, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2768–2775 (2010).
  • [12] Sepahvand H., Addressing control and capacitor voltage balancing challenges in multilevel power electronic converters, PhD Thesis, Faculty of the Graduate School of the MISSOURI University of Science and Technology, Rolla, Missouri, United States (2012).
  • [13] Du Z., Tolbert L.M., Ozpineci B., Chiasson J.N., Fundamental frequency switching strategies of a seven-level hybrid cascaded H-bridge multilevel inverter, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 25–33 (2009).
  • [14] Ismail B., Idris S., Hassan S., Ismail R.C., Haron A.R., Azmi A., Selective Harmonic Elimination of Five-level Cascaded Inverter Using Particle Swarm Optimization, International Journal of Engineering and Technology, vol. 5, pp. 5220–5232 (2014).
  • [15] Wahidah A.H., Nasrudin A.R., Maaspaliza A., Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA, Journal of Power Electronics, vol. 14, pp. 488–498 (2014).
  • [16] Mohammad K.B., Hossein I.E., Frede B., Selective Harmonic Elimination in Asymmetric Cascaded Multilevel Inverters Using a New Low frequency Strategy for Photovoltaic Applications, Electric Power Components and Systems, vol. 43, pp. 964–969 (2015).
  • [17] Halim W.A., Rahim N.A., Azri M., Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel, Inverter Using FPGA, Journal of Power Electronics, vol. 14, no. 3, pp. 488–498 (2014).
  • [18] Babaei E., Farhadi M., Farshid K., Mazgar F., Symmetric and asymmetric multilevel inverter topologies with reduced switching devices, Electric Power Systems Research, vol. 86, pp. 122–130 (2012).
  • [19] Manai L., Armi F., Capacitor voltage balancing control for CHB multilevel inverter considering harmonic distortion based on Programmed Matrix PWM, Journal of Electrical Engineering JEE- vol. 16, no. 3 (2016).
  • [20] Sepahvand H., Liao J., Ferdowsi M., Investigation on Capacitor Voltage Balancing in Cascaded H-Bridge Multilevel Converters with Fundamental Frequency Switching, IEEE Transactions on Industrial Electronics, vol. 58, no. 11 (2011).
  • [21] Armi F., Manai L., Besbes M., FPGA Implementation of Selective Harmonic Elimination Controlled Asymmetrical Cascaded Nine Level Inverter Using Newton Raphson Algorithm, International Conference on Automation, Hammamet, Tunisia (2016).
  • [22] Bakhshizadeh M.K., Eini H.I., Blaabjerg F., Selective Harmonic Elimination in Asymmetric Cascaded Multilevel Inverters Using a New Low-frequency Strategy for Photovoltaic Applications, Electric Power Components and Systems, vol. 43, no. 8-10, pp. 964–969 (2015).
  • [23] Diong B., Sepahvand H., Corzine K.A., Harmonic distortion optimization of cascaded H-bridge inverters considering device voltage drops and non integer DC voltage ratios, IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3106–3114 (2013).
  • [24] Youssef M.Z., Woronowicz K., Aditya K., Abdul A.N., Design and development of an efficient multi-level DC/AC traction inverter for railway transportation electrification, IEEE Transactions on power Electronics, vol. 31, iss. 4 (2016).
  • [25] EL Mehdi Belkacem R., Benzid R., Bouguechal N., Multilevel inverter with optimal THD through the firefly algorithm, Archives of Electrical Engineering, vol. 66, no. 1, pp. 141–154 (2017).
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-9510d660-5186-4a1b-9647-87c9106c4c87
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