FIReWORK: FIR filters hardware structures auto-generator

• Autorzy: Smyk R.
• Języki publikacji: EN

Abstrakty

EN

The paper presents application called FIReWORK, that allows for automatic creation of the VHDL hardware structures of FIR filters. Automatically generated specialized hardware solutions dedicated to the FPGA and ASIC are commonly known as Intellectual Property Cores. The essential future of the application is easy initialization of FIR filter parameters in GUI, and then automatically design, calculate and generate the IP Core structure of the filter. The hardware realization is based on the Residue Number System, as a main arithmetic. Current structure of the application, the main objectives of the project, design assumptions and benefits are discussed.

Słowa kluczowe

EN

FIR filtering; FPGA; hardware generation; IP Core; software generator; VHDL

PL

filtrowanie FIR; FPGA; generacja sprzętowa; IP core; generator oprogramowania; VHDL

• Wydawca: Wydawnictwo Politechniki Łódzkiej
• Czasopismo: Journal of Applied Computer Science
• Rocznik: 2013
• Tom: Vol. 21, nr 1
• Strony: 135--149
• Opis fizyczny: Bibliogr. 13 poz.

Twórcy

autor

Smyk R.

• Gdansk University of Technology, Faculty of Electrical and Control Engineering, G. Narutowicza 11/12, 80-233 Gdansk

Bibliografia

• [1] Smith, J. O., Introduction to Digital Filters with Audio Applications, W3K Publishing, http://books.w3k.org/, 2007, ISBN 978-0-9745607-1-7.
• [2] Cardarilli, G., C. D. R. A. L. R. N. A. R. M., RNS implementation of high performance filter for satellite demultiplexing, Proc. of the 2003 IEEE Aerospace Conference, Vol. 3, 2003, pp. 1365–1379.
• [3] Szabo, N. and Tanaka, R., Residue Arithmetic and its Applications to Computer Technology, McGraw-Hill, New York, 1967.
• [4] Soderstrand, M. e. a., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, New York, 1986.
• [5] Santarin, M., Xilinx Redefines State of the Art With New 7 Series FPGAs, Xcelljournal, Issue 72, 2010, pp. 6–11.
• [6] Xilinx, Intellectual Property, May 2012, http://www.xilinx.com/products/intellectual-property.
• [7] Xilinx, LogiCORE IP Fast Fourier Transform v7.1, Tech. rep., Xilinx, Inc., 2011.
• [8] Xilinx, IP LogiCORE FIR Compiler v5.0, Tech. rep., Xilinx, Inc., 2011.
• [9] Yoo, H., Hardware-efficient distributed arithmetic architecture for high-order digital filters, Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP ’05). IEEE International Conference on, Vol. 5, 2005, pp. 125–128.
• [10] Smyk, R., C. M., FPGA realization of the high-speed binary-to-residue converter, Poznan University of Technology Academic Journals. Electrical Engineering, No. 58, 2008, pp. 65–72.
• [11] Piestrak, S., Design of high-speed residue-to-binary number system converter based on the Chinese Remainder Theorem, Proc. ICCD’94, Int. Conf. on Computer Design: VLSI in Computers and Processors, 1994, pp. 508–511.
• [12] Czyzak, M., An improved high-speed residue-to-binary converter based on the Chinese Remainder Theorem, Pomiary, Automatyka, Kontrola, Vol. 53, No. 4, 2007, pp. 72–75.
• [13] Smyk, R., FIReWORK: Zaawansowany system symulacji i generacji struktur ukladowych filtrow FIR, Wymagania funkcjonalne wersja: 1.2, Tech. rep., Platforma Informatyczna TEWI, Projekt realizowany w ramach dzialania 2.3. PO IG 2007-20013, 2012.