Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

• Autorzy: Dargar Abha , Srivastava Viranjay M.

Identyfikatory

DOI

10.24425/ijet.2021.135940

• Języki publikacji: EN

Abstrakty

EN

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (V_TH1) could be reduced compared to the external gate (V_TH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Słowa kluczowe

EN

short-channel effects; metal oxide semiconductor; transistor; cylindrical surrounding double-gate; dual-material gate; microelectronics; nanotechnology

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2021
• Tom: Vol. 67, No. 1
• Strony: 29--34
• Opis fizyczny: Bibliogr. 20 poz., schem., wykr.

Twórcy

autor

Dargar Abha

• Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban, 4041, South Africa

autor

Srivastava Viranjay M.

• Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban, 4041, South Africa

Bibliografia

• [1] G. E. Moore, “Cramming more components into integrated circuit,” Reprinted from Electronics, vol. 38, no. 8, April 19, 1965, p. 114 in IEEE solid-state circuits society newsletter, vol. 11, no. 3, pp. 33-35, 2006. DOI: 10.1109/N-SSC.2006.4785860.
• [2] K. Roy, K. S. Yeo, “Low voltage, low power VLSI subsystems,” New York: McGraw-Hill, 2005.
• [3] A. Kahn, “Fermi level, work function and vacuum level,” Materials Horizons, vol. 3, no. 1, pp. 7-10, Oct. 2015. DOI: 10.1039/C5MH00160A
• [4] A. Dargar and V. M. Srivastava, “Thickness modeling of short-channel cylindrical surrounding double-gate MOSFET at strong inversion using depletion depth analysis,” Micro and Nanosystems, vol. 12, no. 1, September 2020. DOI: 10.2174/1876402912666200831175936.
• [5] S. Deb, B. N. Singh, N. Islam, and S. K. Sarkar, “Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET,” IEEE Transactions on Nanotechnology, vol. 11, no. 3, pp. 472-478, 2011. DOI: 10.1109/TNANO.2011.2177669
• [6] T. K. Chiang and M. L. Chen, “A new two-dimensional analytical model for short-channel symmetrical dual-material double-gate metal–oxide–semiconductor field effect transistors,” Japanese Journal of Applied Physics, vol. 46, no. 6A, p. 3283-3290, 2007.
• [7] Y. H. Shin, M. S. Bae, C. Park, J. W. Park, H. Park, Y. J. Lee, and I. Yun, “Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects,” Semiconductor Science and Technology, vol. 33, no. 6, pp. 065010(1-8), 2018.
• [8] T. Kim, N. Franklin, C. Srinivasan, P. Kalavade, and A. Goda, “Extreme short-channel effect on RTS and inverse scaling behavior: source–drain implantation effect in 25-nm NAND Flash memory,” IEEE electron device letters, vol. 32, no. 9, pp. 1185-1187, 2011.
• [9] J. P. Colinge, “Multiple gate SOI MOSFETs,” Solid State Electron, vol. 48, no. 6, pp. 897-905, 2004.
• [10] V. M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 10, pp. 1124-1135, 2011.
• [11] L. Naidoo and V. M. Srivastava, “Application of CSDG MOSFET based active high pass filter in satellite communications: A circuit perspective,” International Conference on Advances in Big Data, Computing and Data Communication Systems, 6-7 Aug. 2018, Durban, South Africa, pp. 1-5.
• [12] S. Baishya, A. Mallik, and C. K. Sarkar, “A pseudo two-dimensional subthreshold surface potential model for dual-material gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2520-2525, 2007.
• [13] T. G. James, S. Joseph, and V. Mathew, “The Influence of Metal Gate Work Function on Short Channel Effects in Atomic-layer Doped DG MOSFETs,” Journal of Electron Devices, vol. 8, pp. 310-319, 2010.
• [14] P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “Analytical modeling and simulation for dual metal gate stack architecture cylindrical/surrounded gate MOSFET,” Journal of semiconductor Technology and Science, vol. 12, no. 4, pp. 458-466, 2012.
• [15] S. K. Mohapatra, K. Pradhan, P. K. Sahu, and M. R. Kumar, “The performance measure of GS-DG MOSFET: an impact of metal gate work function,” Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 2, pp. 025002, 2014.
• [16] F. Lagraf, R. Djamil, G. Kamel, and Z. Mourad, “Channel length effect on subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs with High-k Gate Dielectrics,” Journal of Nano and Electronic Physics, vol. 11, no. 2, 2019. DOI: 10.21272/jnep.11(2).02011
• [17] M. R. Hasan, K. Ullah, M. Hossain, T. Hossain, N. F. Rashid, S. Quraishi, and P. Ghosh, “Metal gate work function engineering: sub-nano regime double date MOSFETs,” International Conference on Electrical, Computer and Communication Engineering, CoxsBazar, Bangladesh, 7-9 February 2019, pp. 1-5. DOI: 10.1109/ECACE.2019.8679134
• [18] Y. B. Kim, Challenges for nanoscale MOSFETs and emerging nano-electronics, Trans. on Electrical and Electronic Materials, Vol. 11, 93-105, 2010. DOI: 10.4313/TEEM.2010.11.3.093.
• [19] F. Chaves, D. Jimenez, and J. Sune, “Explicit model for the gate tunneling current in double-gate MOSFETs, Solid-State Electronics, vol. 68, pp. 93-97, 2012. DOI: 10.1016/j.sse.2011.11.003
• [20] A. Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker, and A. Asenov, “Quantum-transport study on the impact of channel length and cross-sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors, IEEE Transaction of Electron Devices, vol. 58, pp. 2209-2217, 2011. DOI: 10.1109/TED.2011.2157929

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).