Study of opencl processing models for FPGA devices

• Autorzy: Szkotak Piotr , Russek Paweł , Wiatr Kazimierz

Identyfikatory

DOI

10.7494/csci.2019.20.1.3114

• Języki publikacji: EN

Abstrakty

EN

In our study, we present the results of the implementation of the SHA-512 algorithm in FPGAs. The distinguished element of our work is that we conducted the work using OpenCL for FPGA, which is a relatively new development method for reconfigurable logic. We examine loop unrolling as an OpenCL performance optimization method and compare the efficiency of the different kernel implementation types: NDRange, Single-Work Item, and SIMD kernels. In our conclusions, we compare the metrics of the created FPGA accelerator to the corresponding GPGPU solutions. Also, our paper is accompanied by a source code repository to allow the reader to follow and extend our survey.

Słowa kluczowe

EN

reconfigurable computing; accelerated computing; high-level hardware synthesis

• Wydawca: Wydawnictwa AGH
• Czasopismo: Computer Science
• Rocznik: 2019
• Tom: Vol. 20 (1)
• Strony: 85--97
• Opis fizyczny: Bibliogr. 19 poz., rys., tab.

Twórcy

autor

Szkotak Piotr

• AGH University of Science and Technology, Krakow, Poland

autor

Russek Paweł

• AGH University of Science and Technology, Krakow, Poland

autor

Wiatr Kazimierz

• AGH University of Science and Technology, Krakow, Poland

Bibliografia

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• [2] Khronos Group. OpenCL overview. https://www.khronos.org/opencl/.
• [3] SHA512AOCLStudy repository, 2018. https://git.plgrid.pl/scm/~plgruss ek/sha512aoclstudy.git.
• [4] Altera Corporation: Altera SDK for OpenCL Getting Started, Version 15.0.0, 2015.
• [5] Altera Corporation: Altera SDK for OpenCL Optimization Guide, Version 15.0.0, 2015.
• [6] Che S., Li J., Sheaffer J.W., Skadron K., Lach J.: Accelerating Compute-Intensive Applications with GPUs and FPGAs. In: 2008 Symposium on Application Specific Processors, pp. 101-107, 2008. http://dx.doi.org/10.1109/SASP.2008.4 570793.
• [7] Ge C., Xu L., Qiu W., Huang Z., Guo J., Liu G., Gong Z.: Optimized Password Recovery for SHA-512 on GPUs. In: 2017 IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC), vol. 2, pp. 226{229, 2017. http://dx.doi.org/10.1109/CSE-EUC.2017.226.
• [8] Hill K., Craciun S., George A., Lam H.: Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA. In: 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 189-193, 2015. http://dx.doi.org/10.1109/ASAP.2015 .7245733.
• [9] Janik I., Khalid M.A.S.: Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL. In: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2016. http://dx.doi.org/10. 1109/MWSCAS.2016.7870147.
• [10] Khronos OpenCL Working Group: The OpenCL Specification, Version 1.0, 2011. https://www.khronos.org/registry/cl/specs/opencl-1.0.pdf.
• [11] National Institute of Standards and Technology: FIPS 180-2, Secure Hash Stan- dard, Federal Information Processing Standard (FIPS), Publication 180-2, Tech. rep., 2002. http://csrc.nist.gov/publications/fips/fips180-2/fips180- 2withchangenotice.pdf.
• [12] Nvidia: Geforce GTX 1080 specification, 2018. https://www.nvidia.com/en- us/geforce/products/10series/geforce-gtx-1080/.
• [13] Russek P.: Data-intensive processing on FPGAs, chap. 2.3, pp. 62-67, AGH University of Science and Technology Press, 2015.
• [14] Russek P., Wiatr K.: The enhancement of a computer system for sorting capabilities using FPGA custom architecture, Computing and Informatics, vol. 32(4), pp. 859-876, 2014.
• [15] Szkotak P., Russek P., Wiatr K.: SHA512AOCLStudy repository, 2018. https: //git.plgrid.pl/scm/~plgrussek/sha512aoclstudy.git.
• [16] Tucci L.D., O'Brien K., Blott M., Santambrogio M.D.: Architectural optimizations for high performance and energy eficient Smith-Waterman implementation on FPGAs using OpenCL. In: Design, Automation Test in Europe Conference Exhibition (DATE), 2017, pp. 716{721, 2017. http://dx.doi.org/10.23919/ DATE.2017.7927082.
• [17] Wang Z., He B., Zhang W., Jiang S.: A performance analysis framework for optimizing OpenCL applications on FPGAs. In: 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 114-125, 2016. http://dx.doi.org/10.1109/HPCA.2016.7446058.
• [18] Wielgosz M., Mazur G., Makowski M., Jamro E., Russek P., Wiatr K.: Analysis of the Basic Implementation Aspects of Hardware-Accelerated Density Functional Theory Calculations, Computing and Informatics, vol. 29(6), pp. 989-1000, 2010. http://www.cai.sk/ojs/index.php/cai/article/viewArticle/125.
• [19] Zohouri H.R., Maruyama N., Smith A., Matsuda M., Matsuoka S.: Evaluating and Optimizing OpenCL Kernels for High Performance Computing with FPGAs. In: SC '16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 409-420, 2016. http://dx.d oi.org/10.1109/SC.2016.34.