Memory resources in hardware implementations of BLAKE and BLAKE2 hash algorithms

• Autorzy: Sugier J.
• Języki publikacji: EN

Abstrakty

EN

In contemporary computer systems security issues are very important for both safety and reliability reasons thus application of appropriate cryptographic methods is a necessity in system design and maintenance. This paper deals with one such method – BLAKE hash function – and investigates its implementation in hardware. The algorithm was a candidate proposed for the SHA-3 contest and, although it was not selected in the final round as the winner, it was very well received for its cryptographic strength and performance, being still used as a hash method of choice in contemporary IT systems. In this paper we discuss a specific modification in hardware realizations of the function which eliminates need for involved data paths distributing message bits among the round units by using auxiliary memory modules for repetitive storage of the message inside each round instance. The idea was implemented in realizations of both BLAKE and BLAKE2 versions of the algorithm in four different organizations: the standard iterative one and three high-speed loop-unrolled architectures with 2, 4 and 5 rounds instantiated in hardware. Together with standard (without RAM) implementations this produced a total of 16 test cases: after implementation in a popular Spartan-3 device from Xilinx their parameters allowed for exhaustive evaluation of the proposed modification. The results reveal that the modification outstandingly enhances size of all the tested architectures: on average, occupation of the FPGA array is reduced at least by half while the improvements in speed, although not so spectacular, are also visible. Additional analyses indicate that the method can also increase overall efficiency of routing, helps in implementation of the loop-unrolled architectures and strengthens optimizations introduced by the BLAKE2 version of the algorithm.

Słowa kluczowe

EN

BLAKE hash algorithm; implementation efficiency; memory; loop unrolling; resource utilization

• Wydawca: Polskie Towarzystwo Bezpieczeństwa i Niezawodności
• Czasopismo: Journal of Polish Safety and Reliability Association
• Rocznik: 2017
• Tom: Vol. 8, No. 1
• Strony: 119--128
• Opis fizyczny: Bibliogr. 13 poz., rys., tab., wykr.

Twórcy

autor

Sugier J.

• Wrocław University of Science and Technology, Faculty of Electronics, Poland

Bibliografia

• [1] Aumasson, J.-P., Henzen, L., Meier, W. & Phan, R.C.-W. (2010). SHA-3 proposal BLAKE, version 1.3. https://www.131002.net/blake/blake.pdf; accessed: March 2017.
• [2] Aumasson, J.-P., Neves, S., Wilcox-O’Hearn, Z., & Winnerlein, C. (2013). BLAKE2: simpler, smaller, fast as MD5. Jacobson M., Locasto M., Mohassel P., Safavi-Naini R. (eds) Applied Cryptography and Network Security ACNS 2013. Springer LNCS, 7954, 119-135.
• [3] Bernstein, D.J. (2008). ChaCha, a variant of Salsa20 http://cr.yp.to/chacha/chacha-20080128 .pdf; accessed: March 2017.
• [4] Bernstein, D.J. (2008). The Salsa20 Family of Stream Ciphers. Robshaw M., Billet O. (eds) New Stream Cipher Designs. Springer LNCS 4986.
• [5] Dunkelman, O., & Biham, E. (2006). A framework for iterative hash functions: Haifa. 2nd NIST Cryptographich Hash Workshop, 22.
• [6] Gaj, K., Homsirikamol, E., Rogawski, M., Shahid, R. & Sharif, M. U. (2012). Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs. The Third SHA-3 Candidate Conference, Washington, DC, USA.
• [7] Gaj, K., Southern, G., & Bachimanchi, R. (2007). Comparison of hardware performance of selected Phase II eSTREAM candidates. Proc. State of the Art of Stream Ciphers Workshop, eSTREAM, ECRYPT Stream Cipher Project, Report, 26, p. 2007.
• [8] Junkg, B. & Apfelbeck, J. (2011). Area-efficient FPGA implementations of the SHA-3 finalists. 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 235241.
• [9] Sugier, J. (2015). Popular FPGA Device Families in Implementation of Cryptographic Algorithms. Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds.) Theory and Engineering of Complex Systems and Dependability. Proc. 11th Int. Conf. Dependability and Complex Systems DepCoS-RELCOMEX. Springer AISC, 365, 485-495.
• [10] Sugier, J. (2016). Implementation Efficiency of BLAKE and Other Contemporary Hash Algorithms in Popular FPGA Devices. Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds.) Proc. 11th Int. Conf. Dependability and Complex Systems DepCoSRELCOMEX. Springer AISC, 470, 457-467.
• [11] Sugier, J. (2016). Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays. J. Polish Safety and Reliability Association, 7(1), 193-200.
• [12] Sugier, J. (2017). Simplifying FPGA Implementations of BLAKE Hash Algorithm with Block Memory Resources. Procedia Engineering, 178, 33-41.
• [13] Xilinx, Inc. (2009). Spartan-3 Family Data Sheet. www.xilinx.com (ds099.pdf); accessed: March 2017.

Uwagi

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).