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Analog circuits specification driven testing by the means of digital stream and non-linear estimation model optimized evolutionarily

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EN
Abstrakty
EN
The method described in this work allows to determine the optimal distribution of pulses of digital signal as well as the non-linear mathematical model based on a multiple regression statistical analysis, which are specialized to an effective and low-cost testing of functional parameters in analog electronic circuits. The aim of this concept is to simplify the process of analog circuit specification validation and minimize hardware implementation, time and memory requirements during the testing stage. This strategy requires simulations of the analyzed analog electronic circuit; however, this effort is done only once – before the testing stage. Then, validation of circuit specification can be obtained after a quick, very low-cost procedure without time consuming computations and without expensive external measuring equipment usage. The analyzed test signature is a time response of the analog circuit to the stream of digital pulses for which distributions were determined during evolutionary optimization cycles. Besides, evolutionary computations assure determination of the optimal form and size of the non-linear mathematical formula used to estimate specific functional parameters. Generally, the obtained mathematical model has a structure similar to the polynomial one with terms calculated by means of multiple regression procedure. However, a higher ordered polynomial usage makes it possible to reach non-linear estimation model that improves accuracy of circuit parametric identification. It should be noted that all the evolutionary calculations are made only at the before test stage and the main computational effort, for the analog circuit specification test design, is necessary only once. Such diagnosing system is fully synchronized by a global digital signal clock that precisely determines time points of the slopes of input excitation pulses as well as acquired output signature samples. Efficiency of the proposed technique is confirmed by results obtained for examples based on analog circuits used in previous (and other) publications as test benchmarks.
Rocznik
Strony
1283--1299
Opis fizyczny
Bibliogr. 35 poz., rys., tab.
Twórcy
autor
  • Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland
  • Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland
Bibliografia
  • [1] J.L. Huertas, “Test and design for testability of analog and mixed-signal IC: theoretical basic and pragmatical approaches”, in European Conference On Circuit Theory And Design, Davos, Switzerland, 1993, pp. 75–156.
  • [2] L. Milorand and A.L. Sangiovanni-Vincentelli, “Minimizing production test time to detect faults in analog circuits”, IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 13 (6), 796–813 (1994).
  • [3] K. Baker, A.M. Richardson, and A.P. Dorey, “Mixed signal test-techniques, applications and demands”, in IEE Proceedings - Circuits, Devices and Systems 143 (6), 358–365, 1996, doi: 10.1049/ip-cds:19960904.
  • [4] A. Milne, D. Taylor, and K. Naylor, “Assessing and comparing fault coverage when testing analogue circuits”, in IEE Proceedings – Circuits, Devices and Systems 144 (1), 1–4, 1997, doi: 10.1049/ip-cds:19970870.
  • [5] J. Savir and Z. Guo, “Test Limitations of Parametric Faults In Analog Circuits”, IEEE Trans. Instrum. Meas. 52 (5), 1444–1454 (2003).
  • [6] M. Tadeusiewicz, S. Hałgas, and M. Korzybski, “Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances”, Int. J. Circuit Theory Appl. 40 (10), 1041–1052 (2012).
  • [7] D. Grzechca, T. Golonek, and J. Rutkowski, “Analog Fault AC Dictionary Creation – The Fuzzy Set Approach”, in IEEE International Symposium on Circ. and Syst., Kos, Greece, 2006, pp. 5744–5747.
  • [8] M. Tadeusiewicz and S. Hałgas, “A method for multiple soft fault diagnosis of linear analog circuits”, Measurement, 131, 714–722 (2019).
  • [9] M. Tadeusiewicz and S. Hałgas, “Soft fault diagnosis of linear circuits with the special attention paid to the circuits containing current conveyors”, AEU-Int. J. Electron. Commun. 115 (2019).
  • [10] H. Dai and M. Souders, “Time domain testing strategies and fault diagnosis for analog systems”, in IEEE Instrumentation and Measurement Technology Conference, 1989, pp. 293–298.
  • [11] A. Balivada, J. Chen, and J.A. Abraham, “Analog testing with time response parameters”, IEEE Des. Test Comput. 13(2), 18–25 (1996).
  • [12] Ł. Chruszczyk and J. Rutkowski, “Specialised excitation and wavelet feature extraction in fault diagnosis of analog electronic circuits”, in IEEE International Conference on Electronics, Circuits and Systems, Malta, 2008, pp. 242–246.
  • [13] S. Temich, T. Golonek, and D. Grzechca, “Design an Identification Function to Reduce the Computational Resources on the Testing Process of an Analog Electronic Circuit”, Elektron. Elektrotech. 25 (3), 25–33 (2019).
  • [14] D. Grzechca and Ł. Chruszczyk, “Wavelet – Neural Network to Analog Paramteric Fault Circuit Location”, 13-th International Mixed Signals Testing Workshop and 3rd GHz/Gbps Test Workshop, Povoa de Varzim, Portugal, 2–6 (2007).
  • [15] S. Hałgas, “Multiple soft fault diagnosis of nonlinear circuits using the fault dictionary approach”, Bull. Pol. Ac.: Tech. 56 (1), 53–57 (2008).
  • [16] P. Jantos, D. Grzechca, and J. Rutkowski, “Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits”, Bull. Pol. Ac.: Tech. 60 (1), 133–142 (2012).
  • [17] M. Woźniak and D. Połap, “On Some Aspects of Genetic and Evolutionary Methods for Optimization Purposes”, Int. J. Electron. and Telecomm. (IJET), 61 (1), 7–16 (2015).
  • [18] M. Tadeusiewicz and S. Hałgas, “A fault verification method for testing of analogue electronic circuits”, Metrol. Meas. Syst., 25 (2), 331–346 (2018).
  • [19] M. Tadeusiewicz and S. Hałgas, “A method for fault diagnosis of nonlinear circuits”, Compel-Int. J. Comp. Math. Electr. Electron. Eng. 38 (6), 1770–1781 (2019).
  • [20] D.E. Goldberg, Genetic Algorithms in Search, Optimization & Machine Learning, Addison-Wesley, 1989.
  • [21] Z. Michalewicz, Genetic Algorithms + Data Structures = Evolution Programs, Springer-Verlag, 1996.
  • [22] D. MacKay, Information Theory, Inference and Learning Algorithms, CUP, 2003.
  • [23] T. Golonek and J. Rutkowski, “Genetic-algorithm-based method for optimal analog test points selection”, IEEE Trans. Circuits Syst. II-Express Briefs 54 (2), 117–121 (2007).
  • [24] T. Golonek and J. Machniewski, “Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations”, Circuits Syst. Signal Process. 37 (7), 2736–2771 (2018).
  • [25] P.N. Variyam, S. Cherubal, and A. Chatterjee, “Prediction of analog performance parameters using fast transient testing”, IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 21(3), 349–361 (2002).
  • [26] P.N. Variyam and A. Chatterjee, “Specification-driven test generation for analog circuits”, IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 19 (10), 1189–1201 (2000). doi: 10.1109/43.875320.
  • [27] D. De Venuto, E. Cantatore, G. Gramegna, C. Marzocca, and F. Corsi, “An Approach to the Specification Driven Testing of Analogue Circuits”, IEEE Mediterranean Electrotechnical Conference on Industrial Applications in Power Systems, Computer Science and Telecommunications, Italy, 1283–1286 (1996).
  • [28] A. Sen and M. Srivastava, Regression Analysis – Theory, Methods, and Applications, Springer-Verlag, Berlin, 2011.
  • [29] B. Kamińska et al., “Analog and mixed-signal benchmark circuits – first release”, in IEEE International Test Conference, Washington, USA, 1997, pp. 183–190.
  • [30] R. Kondagunturi, E. Bradley, K. Maggard, and C. Stroud, “Benchmark circuits for analog and mixed-signal testing”, in IEEE Southeastcon 99 Conference on Technology on the Brink of 2000, Lexington, 1999, pp. 217–220.
  • [31] B. Long, M. Li, H. Wang, and S. Tian, “Diagnostics of analog circuits based on LS-SVM using time domain features”, Circuits Syst. Signal Process. 32 (6), 2683–2706 (2013).
  • [32] A.D. Spyronasios, M.G. Dimopoulos, and A.A. Hatzopoulos, “Wavelet Energy-based Mahalanobis Distance Metric for Testing Analog and Mixed-Signal Circuits”, in IEEE International Conference Mixed Design of Integrated Circuits and Systems, Warsaw, 2010, pp. 218–224.
  • [33] S.R. Das et al., “Testing analog and mixed-signal circuits with built-in hardware – A new approach”, in IEEE Trans. Instrum. Meas. 56 (3), 840–855 (2007).
  • [34] T.R. Balen, J.V. Calvano, M.S. Lubaszewski, and M. Renovell, “Built-in self-test of field programmable analog arrays based on transient response analysis”, J. Electron. Test.-Theory Appl. 23 (6), 497–512 (2007).
  • [35] M. Lubaszewski and J.L. Huertas, “Test and Design-for-Test of Mixed-Signal Integrated Circuits”, in Information Technology, R. Reis (Ed.), vol. 157, IFIP International Federation for Information Processing, Springer, Boston, 2004, pp. 183–212.
Uwagi
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-87ef9921-5534-4add-82a1-562872890514
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