Basic 3D graphics processor implemented on small FPGA

• Autorzy: Panek K. , Flak B. , Koryciak S. , Wiatr K.
• Języki publikacji: EN

Abstrakty

EN

FPGAs have big computing possibilities and therefore are very popular as dedicated hardware accelerators. A few years ago, FPGAs were expensive and the cheapest ones had very limited capabilities, because of small amount of logic elements and slow internal clocks. Nowadays, cheap development boards are available at a price below 50€ with abilities to transmit even HDMI signals. This paper covers implementation of the soft processor with a 3D graphics coprocessor on the cheapest available FPGA board with HDMI connector, containing only 8k Logic Elements.

Słowa kluczowe

EN

FPGA; Verilog; 3D graphic; HDMI; Bresenham’s line; algorithm; perspective projection

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2018
• Tom: Vol. 64, No. 1
• Strony: 8--10
• Opis fizyczny: Bibliogr. poz., 10, rys., tab., wzory

Twórcy

autor

Panek K.

• AGH University of Science an Technology, 30 Mickiewicza Ave, Cracow, Poland

autor

Flak B.

• AGH University of Science an Technology, 30 Mickiewicza Ave, Cracow, Poland

autor

Koryciak S.

• AGH University of Science an Technology, 30 Mickiewicza Ave, Cracow, Poland

autor

Wiatr K.

• AGH University of Science an Technology, 30 Mickiewicza Ave, Cracow, Poland

Bibliografia

• [1] Barszczowski M., Koryciak S., Dąbrowska-Boruch A., Wiatr K.: Communication with n-gram hashing hardware accelerator for the ARM using ACP. Measurement Automation Monitoring, vol. 60, no. 7, pp. 486-488, 2014.
• [2] Intel, Avalon® Interface Specifications, MNL-AVABUSREF, 2017.05.08.
• [3] Kamami, maXimator - Altera MAX10 FPGA development board, http://maximator-fpga.org/ (09.2017).
• [4] Intel, RS232 UART for Altera DE-Series Boards, ftp://ftp.altera.com/up/pub/Intel_Material/16.1/University_Program_I P_Cores/Communication/RS232.pdf (09.2017).
• [5] Łukawski G., Lasota M., Michno T.: Rzutowanie równoległe i perspektywiczne, http://achilles.tu.kielce.pl/Members/dkaczmarski/ studia-dzienne/grafika_2d_lab7.pdf (09.2017).
• [6] Bresenham's line algorithm, https://en.wikipedia.org/wiki/ Bresenham%27s_line_algorithm (09.2017).
• [7] David Rousset, Tutorial part 2: learning how to write a 3D soft engine from scratch in C#, TS or JS – drawing lines & triangles, https://www.davrous.com/2013/06/14/tutorial-part-2-learning-how-towrite- a-3d-soft-engine-from-scratch-in-c-ts-or-js-drawing-linestriangles/ (09.2017).
• [8] Fpga4fun.com, HDMI, http://www.fpga4fun.com/HDMI.html (09.2017).
• [9] HDMI Founders, HDMI Specification 1.3a, https:// www.microprocessor.org/HDMISpecification13a.pdf (09.2017).
• [10] Blender.org, Open source 3D creation, https://www.blender.org/ (09.2017).

Uwagi

EN

1. This research is supported by statutory founds of AGH UST, Department of Computer Science, Electronics and Telecommunication. No. 11.11.230.017.

PL

2. Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).