A Gigabit Ethernet interface with an embedded lossless data encoder on FPGA

• Autorzy: Dulnik G. , Grzelka A. , Łuczak A.
• Języki publikacji: EN

Abstrakty

EN

This paper proposes a high speed data encoder, which is dedicated to encode data sent by a gigabit Ethernet interface. The main aim of this encoder is not to achieve high bitrate reduction, but to create the coder, which can be efficiently implemented on FPGA and easily modified according to different content. This encoder can be added to existing systems and greatly reduce the network load by a small change in the FPGA project design.

Słowa kluczowe

EN

FPGA; encoder; Gigabit Ethernet

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2015
• Tom: Vol. 61, No. 7
• Strony: 364--366
• Opis fizyczny: Bibliogr. 6 poz., rys., schem., tab., wykr.

Twórcy

autor

Dulnik G.

• Chair of Multimedia Telecommunications and Microelectronics, Poznań University of Technology, 3 Polanka St., 60-965 Poznań, Poland

autor

Grzelka A.

• Chair of Multimedia Telecommunications and Microelectronics, Poznań University of Technology, 3 Polanka St., 60-965 Poznań, Poland

autor

Łuczak A.

• Chair of Multimedia Telecommunications and Microelectronics, Poznań University of Technology, 3 Polanka St., 60-965 Poznań, Poland

Bibliografia

• [1] Alachiotis N., Berger S. A., Stamatakis A.: Efficient PC-FPGA Communication over Gigabit Ethernet, CIT, Munich, 2010.
• [2] Postel J.: User Datagram Protocol, RFC 768 (Standard). Internet Engineering Task Force, August 1980.
• [3] Postel J.: Internet Protocol, RFC 791 Standard. Internet Engineering Task Force, Sep-tember 1981.
• [4] IEEE Std 802.3-2012, IEEE Standard for Ethernet, New York, December 2012.
• [5] Domański M.: Obraz cyfrowy, WKiŁ, Warsaw, 2010.
• [6] Thiele C., Vizzotto B., Martins A., Rosa V., Bampi S.: A low-cost and high efficiency entropy encoder architecture for H.264/AVC, VLSI-SoC, Santa Cruz, 2012.