Efficient transient simulation of efuse

• Autorzy: Jaworski Zbigniew

Identyfikatory

DOI

10.24425/ijet.2025.153636

• Języki publikacji: EN

Abstrakty

EN

This paper presents a novel approach to model effuse device. An efuse is a simple semiconductor device which can be referred to as a programmable resistor and is available in many modern CMOS technologies. The efuse resistance can be changed by burning procedure, i.e. applying specific electric current value for particular time. The new efuse resistance is retained permanently. The typical efuse application is one-time programmable (OTP) memory. However, process design kits do not provide any model covering the transition from initial to burned state. Thus, verification of programming of an OTP cell is practically impossible. To address this problem, a behavioral Verilog-A model of efuse has been developed. This paper presents the model and its application to verify the example OTP cell designed in 22 nm FD-SOI technology. The proposed model is easy to use and to allow for effective transient simulation of efuse-based designs.

Słowa kluczowe

EN

Efuse; Verilog-A; transient simulation; OTP memory; FD SOI; CMOS

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2025
• Tom: Vol. 71, No. 3
• Strony: 29
• Opis fizyczny: Bibliogr. 26 poz., rys. tab.

Twórcy

autor

Jaworski Zbigniew

• Warsaw University of Technology

Bibliografia

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Uwagi

1. Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki (2025).

2. This work has been supported by the OCEAN12 (Opportunit to Carry European Autonomous driviNg further with FD-SOI technology up to 12 nm node).