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Probabilistic elements in analysis of performance of multiprocessor systems

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The paper presents important probabilistic elements that should be taken into consideration in the analysis of performance of classical multiprocessor systems. These elements represent the following quantities: modified arrival rate for processor requests and a few probabilities, which determine the frequency of certain events when a multiprocessor system is working. There are four peculiar events: service of another job, existence of the queue, a processor request while the given task is waiting into the queue and the return of another task into the queue while the given task is waiting in the queue. The first three events happen more often when a system consists of less number of processors, whereas the fourth event happens more often when more processors work in a system. Including (or not) the probabilities of these events to the analysis of performance of multiprocessor systems exerts its much influence on the precision of computations. All the mentioned quantities were described in detail. Formulas for these quantities were derived. Examples of applications of the formulas to the prediction of performance of various multiprocessor systems were presented.
Rocznik
Strony
765--771
Opis fizyczny
Bibliogr. 22, rys., tab., wykr.
Twórcy
autor
  • Silesian University of Technology, Department of Electronics, 16 Akademicka St., 44-100 Gliwice, Poland
  • Silesian University of Technology, Department of Electronics, 16 Akademicka St., 44-100 Gliwice, Poland
Bibliografia
  • [1] E. Berg, H. Zeffer, and E. Hagersten, “A statistical multiprocessor cache model”, IEEE Int. Symp. on Performance Analysis of Systems & Software 1, 89-99 (2006).
  • [2] Chi Xu, Xi Chen, R.P. Dick, and Z.M. Mao, “Cache contention and application performance prediction for multi-core systems”, IEEE Int. Symp. on Performance Analysis of Systems & Software 1, 76-86 (2010).
  • [3] J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, and C. Kozyrakis, “Comparative evaluation of memory models for chip multiprocessors”, ACM Trans. on Architecture and Code Optimization 5 (3), CD-ROM (2008).
  • [4] P. Prieto, V. Puente, and J.-A. Gregorio, “Multilevel cache modeling for chip-multiprocessor systems”, Computer Architecture Letters 10 (2), 49-52 (2011).
  • [5] Kim Jongioon and A. El-Amawy, “Performance and architectural features of segmented multiple bus system”, Int. Conf. on Parallel Processing 1, 154-161 (1999).
  • [6] C.-H. Tung and C.W. McCarron, “Analysis of a multiple bus multiprocessor”, 26th Asilomar Conf. on Signals, Systems and Computers 2, 925-929 (1992).
  • [7] I. Assayad and S. Yovine, “Performance analysis of embedded multiprocessor industrial applications: methodology and tools”, 14th IEEE Int. Conf. Electronics, Circuits and Systems 1, 907-910 (2007).
  • [8] S. Manolache, P. Eles, and Zebo Peng, “Schedulability analysis of multiprocessor real-time applications with stochastic task execution times”, ACM Int. Conf. on Computer Aided Design 1, 699-706 (2002).
  • [9] J. Rosen, A. Andrei, P. Eles, and Zebo Peng, “Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip”, 28th IEEE Int. Real-Time Systems Symp. 1, 49-60 (2007).
  • [10] A. Kumar, B. Mesman, H. Corporaal, and Yajun Ha, “Iterative probabilistic performance prediction for multi-application multiprocessor systems”, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems 29 (4), 538-551 (2010).
  • [11] E. Gelenbe, Multiprocessor Performance, John Wiley & Sons Ltd., Chichester, 1989.
  • [12] D.G. Kendall, “Some Problems in the Theory of Queues”, J. Royal Statistical Society B 13, 151-185 (1951).
  • [13] T. Czachórski, Queueing Models in Performance Evaluation of Computer Networks and Systems, Jacek Skalmierski’s Computer Workshop, Gliwice, 1999, (in Polish).
  • [14] K. Taborek, Arbitration Circuits for Multi-processor Systems, Doctor’s Thesis, Silesian Technical University, Gliwice, 2003, (in Polish).
  • [15] S. Lavenberg, Computer Performance Modeling Handbook, Academic Press, New York, 1983.
  • [16] K. Taborek, “An Analytical method of performance prediction of multiprocessor systems”, Electrical Review 10, 72-75 (2011), (in Polish).
  • [17] K. Taborek and E. Hrynkiewicz “A multiprocessor system for arbitration circuit examination - hardware implementation”, Electronics 9 (LI), 48-51 (2010), (in Polish).
  • [18] K. Taborek and Z. Pogoda, “Irregular load of processors in multiprocessor system”, Electronics 10 (L), 60-63 (2009), (in Polish).
  • [19] K. Taborek and E. Hrynkiewicz, “Arbitration circuit with cyclically shifted priorities for multi-processor system”, 3rd Int. IFAC Workshop on Discrete-Event System Design 1, CD-ROM (2006).
  • [20] M. Frankiewicz and A. Kos, “Overheat protection circuit for high frequency processors”, Bull. Pol. Ac.: Tech. 60 (1), 55-59 (2012).
  • [21] K. Taborek, “An analytical method for activity description of arbitration circuits with rotation of priorities”, Electronics 10 (LIII), 76-78 (2012), (in Polish).
  • [22] Thing-Fong Tsuei and M.K. Vernon, “A Multiprocessor Bus Design Model Validated by System Measurement”, IEEE Trans. on Parallel and Distributed Systems 6 (3), 712-727 (1992).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-8413907e-3ad5-4c10-af26-7215860aedbf
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