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Abstrakty
High-level languages (HLL) for defining hardware implementation are important in both academic and commercial research. Impulse C could be an example of such language. This environment provides a programming model and library of functions for parallel applications, targeting FPGA-based platforms with the ability to partition the algorithm between software and hardware. This article’saim is to briefly describe DVCPRO HD, one of the intra-frame video-coding algorithms widely used in consumer equipment. DVCPRO HD is a DCT -based lossy video coding algorithm which uses variable-length coding (VLC) and runlength encoding (RLE) to achieve a 5:1 compression ratio. This paper presents DVCPRO HD video-coding-standard principles as well as decoder implementation working in real-time, compliant with the afore-mentioned standard and implemented in Impulse C. According to the authors’ knowledge, the presented solution is the first FPGA implementation of this coding standard which includes all three VLC stages of data re-arrangement. What is more, this is the first DVCPRO HD implementation which utilizes Impulse C.
Wydawca
Czasopismo
Rocznik
Tom
Strony
531--546
Opis fizyczny
Bibliogr. 25 poz., rys., tab.
Twórcy
autor
- AGH University of Science and Technology, Krakow, Poland
autor
- AGH University of Science and Technology, Krakow, Poland
Bibliografia
- [1] CENELEC: Recording — Helical-scan digital video cassette recording system using 6,35 mm magnetic tape for consumer use (525-60, 625-50, 1125-60 and 1250-50 systems). Part 2: SD format for 525-60 and 625-50 systems (IEC 61834-2:1998), 1998.
- [2] Chen W. H., Smith C. H., Fralick S. C.: A fast computational algorithm for the discrete cosine transform. IEEE Transactions on Communications, vol. 25, pp.1004–1009, 1977.
- [3] Cheung N. M., Fan X., O. C. A., Kung M. C.: Video Coding on Multicore Graphics Processors.IEEE Signal Processing Magazine, vol. 27, pp. 79–89, 2010.
- [4] Cichoń S., Gorgoń M., Pac M.: Handel-C design enhancement for FPGA-based DV decoder. Reconfigurable Computing Architectures and Applications, Lecture Notes in Computer Science, LNCS, pp. 128–133, 2006.
- [5] DRC Computing: Accelium Coprocessors Product Datasheet webpage, 2013.
- [6] Eijndhoven van J., Sijstermans F.: Data Processing Device and method of Computing the Cosine Transform of a Matrix, Patent WO 9948025, 1999.
- [7] Gorgoń M.: Architektury rekonfigurowalne do przetwarzania i analizy obrazu oraz dekodowania cyfrowego sygnału wideo. UWND AGH, Kraków, 2007.
- [8] Greisen P., Heinzle S., Gross M., Burg A P.: An FPGA-based processing pipe-line for high definition stereo video. EURASIP Journal on Image and Video Processing, 2011.
- [9] Hsiao Y. M., Chang F. P., Chu Y. S.: High speed multimedia network ASIC design for H.264/AVC. In: The 5th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2010.
- [10] Huang H. J., Fang C. H., Fan C. P.: Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications. IET Image Processing, vol. 6, pp. 104–114, 2012.
- [11] Impulse Accelerated: CoDeveloper User Guide, 2013.
- [12] Kalali E., Adibelli Y., Hamzaoglu I.: A high performance and low energy intra prediction hardware for HEVC video decoding. In: Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012.
- [13] Kim S., Kim H., Chung T., Kim J. G.: Design of H.264 video encoder with C to RTL design tool. In: International SoC Design Conference (ISOCC), 2012.
- [14] Kinsman A. B., Nicolici N.: A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, pp. 499–503, 2011.
- [15] Lee C., Yang S.: Design of an H.264 decoder with variable pipeline and smart bus arbiter. In: International SoC Design Conference (ISOCC), 2010.
- [16] Loeffler C., Ligtenberg A., Moschytz G.: Practical Fast 1-DCT Algorithms with 11 Multiplications. In: Proc. of the International Conference on Acoustics, Speech, and Signal Processing, pp. 988–991, 1989.
- [17] MainConcept: TotalCode Studio webpage, 2013.
- [18] Pieters B., De Cock J., Hollemeersch C., Wielandt J., Lambert P., Van de Walle R.: Ultra High Definition video decoding with Motion JPEG XR using the GPU. In: 18th IEEE International Conference on Image Processing (ICIP), 2011.
- [19] Rodriguez R., Martinez J. L., Fernandez-Escribano G., Claver J. M., Sanchez J. L.: Accelerating H.264 inter prediction in a GPU by using CUDA. In: International Conference on Consumer Electronics (ICCE), 2010.
- [20] Shan J., Chen C., and Yang E.: High performance 2-D IDCT for Image/Video Decoding based on FPGA. In: International Conference on Audio, Language and Image Processing (ICALIP), 2012.
- [21] Shou-Gen X., Ming-Jiang W., Shi-Kai Z.: A new hardware architecture for H.264 intra prediction frame processing. In: IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application (IMSAA), 2011.
- [22] SMPTE: SMPTE 314M: Data Structure for DV-based Audio, Data and Compressed Video 25 and 50 Mb/s, 1999.
- [23] SMPTE: SMPTE 370M: Data Structure for DV-Based Audio, Data and Compressed Video at 100 Mb/s 1080/60i, 1080/50i, 720/60p, 720/50p, 2006.
- [24] SourceForge: Libdv webpage, 2006.
- [25] Staworko M., Modrzyk D.: A high-performance VLSI architecture of 2D DWT processor for JPEG2000 encoder. In: Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011.
Typ dokumentu
Bibliografia
Identyfikator YADDA
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