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High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic

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EN
Abstrakty
EN
Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency - Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. Distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using Distributed Arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.
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Twórcy
  • Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India
  • Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India
  • Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India
  • Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India
Bibliografia
  • [1] H. Kim and S. Lekcharoen, “A Cooley-Tukey modified algorithm in fast Fourier transform,” The Korean Journal of Mathematics, vol. 19, no. 3, 2011.
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  • [4] R. Gonzalez-Toral, P. Reviriego, J. A. Maestro, and Z. Gao, “A scheme to design concurrent error detection techniques for the fast Fourier transform implemented in sram-based fpgas,” IEEE Transactions on Computers, vol. 67, no. 7, pp. 1039–1045, 2018.
  • [5] K. K. Parhi, VLSI digital signal processing systems: design and implementation. John Wiley & Sons, 2007.
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  • [8] S. Patel, “Design and implementation of 31-order fir low-pass filter using modified distributed arithmetic based on fpga,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 2, no. 10, pp. 650–656, 2013.
  • [9] S. Venkatachalam and S.-B. Ko, “Approximate sum-of-products designs based on distributed arithmetic,” IEEE Transactions on very large scale integration (VLSI) systems, vol. 26, no. 8, pp. 1604–1608, 2018.
  • [10] K. N. Bowlyn and N. M. Botros, “A novel distributed arithmetic multiplierless approach for computing complex inner products,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA). The Steering Committee of The World Congress in Computer Science, Computer, 2015, p. 606.
  • [11] E. E. Swartzlander and C. E. Lemonds, Computer Arithmetic: Volume III. World Scientific, 2015.
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  • [13] A. K. Y. Reddy and S. P. Kumar, “Performance analysis of 8-point fft using approximate radix-8 booth multiplier,” in 2018 3rd International Conference on Communication and Electronics Systems (ICCES). IEEE, 2018, pp. 42–45.
  • [14] A. Ajay and R. M. Lourde, “Vlsi implementation of an improved multiplier for fft computation in biomedical applications,” in 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2015, pp. 68–73.
  • [15] N. M. Sk et al., “Multi-mode parallel and folded vlsi architectures for 1d-fast Fourier transform,” Integration, vol. 55, pp. 43–56, 2016.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-7f3beebf-b9a5-412a-bd86-020e14af4902
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