A New 13-Level Switched-Capacitor Inverter with Reduced Device Count

• Autorzy: Jena Kasinath , Panigrahi Chinmoy Kumar , Gupta Krishna Kumar

Identyfikatory

DOI

10.2478/pead-2021-0005

• Języki publikacji: EN

Abstrakty

EN

This paper proposed a new voltage-boosting 13-level switched-capacitor (SC) cost-effective inverter. The proposed topology comprises fourteen transistors, three capacitors and a single DC source to produce a 13-level staircase waveform. The capacitor voltage balancing problem is inherently solved by the series/parallel technique. Structural description, working principle, calculation of optimum values of capacitance and modulation scheme are briefly described. The comparative analyses with the existing SC multilevel inverter (MLI) in terms of voltage gain, blocking voltage, total standing voltage (TSV), component per level factor and cost function illustrate the merits of the proposed topology. Further, simulation and experimental results at different loading conditions verify the feasibility of the proposed topology.

Słowa kluczowe

EN

multilevel inverter; switched capacitor; voltage gain; component per level factor; cost function

• Wydawca: De Gruyter
• Czasopismo: Power Electronics and Drives
• Rocznik: 2021
• Tom: Vol. 6 (41)
• Strony: 26--41
• Opis fizyczny: Bibliogr. 24 poz., rys., tab.

Twórcy

autor

Jena Kasinath

• School of Electrical Engineering, KIIT Deemed to be University, Bhubaneswar, India

autor

Panigrahi Chinmoy Kumar

• School of Electrical Engineering, KIIT Deemed to be University, Bhubaneswar, India

autor

Gupta Krishna Kumar

• THAPAR University, Patiala, India

Bibliografia

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