PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Tytuł artykułu

Spiking Neural Network Based on Cusp Catastrophe Theory

Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This paper addresses the problem of effective processing using third generation neural networks. The article features two new models of spiking neurons based on the cusp catastrophe theory. The effectiveness of the models is demonstrated with an example of a network composed of three neurons solving the problem of linear inseparability of the XOR function. The proposed solutions are dedicated to hardware implementation using the Edge computing strategy. The paper presents simulation results and outlines further research direction in the field of practical applications and implementations using nanometer CMOS technologies and the current processing mode.
Rocznik
Strony
273--284
Opis fizyczny
Bibliogr. 20 poz., rys., tab.
Twórcy
  • Institute of Computing Science, Poznań University of Technology, Poznań
  • Institute of Computing Science, Poznań University of Technology, Poznań
autor
  • Universidade Nova de Lisboa, 2829-516 Caparica, Portugal
Bibliografia
  • [1] Chen D.D., Chen X.J., Zhang K., An Exploratory Statistical Cusp Catastrophe Model, IEEE International Conference on Data Science and Advanced Analytics, pp. 100-109, 2016.
  • [2] Cheng H.-P. et al., Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective, Design, Automation & Test in Europe Conference & Exhibition, IEEE, 2017.
  • [3] Davis M. et al, Loihi, Neuromorphic Manycore Processor with On-Chip Learning, IEEE Micro, vol. 38, Issue 1, pp. 82-99, 2018.
  • [4] Enríquez-Gaytán J., Gómez-Castañeda F., Moreno-Cadenas J.A., Flores-Nava L.M., Experimental Spiking Neural Network: Solving the XOR Paradigm with Metaheuristics, 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico, 2018.
  • [5] Esposito C., Castiglione A., Pop F., Choo K.R., Challenges of Connecting Edge and Cloud Computing: A Security and Forensic Perspective, IEEE Cloud Computing, vol. 4, no. 2, pp. 13-17, March-April 2017.
  • [6] Frenkel Ch. et al., A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28 nm CMOS, IEEE Transactions on Biomedical Circuits and Systems, 2018.
  • [7] Luo Q. Fu, Y., Liu J., Qiu J. Bi, S., Cao Y., Ding X., Improving Learning Algorithm Performance for Spiking Neural Networks, 17th IEEE International Conference on Communication Technology, 2017.
  • [8] Hodgkin A.L., Huxley A.F., A quantitative description of membrane current and its application to conduction and excitation in nerve, The Journal of Physiology, vol. 117, pp. 500-544, 1952.
  • [9] Chang R., Hu, S., Wang H., Huang J.He, Q., Efficient Multispike Learning for Spiking Neural Networks Using Probability-Modulated Timing Method, IEEE Transactions on Neural Networks and Learning Systems, 2018.
  • [10] Izhikevich E.M., Simple Model of Spiking Neurons, IEEE Transactions on Neural Networks, vol. 14, no. 6, pp. 1569-1572, 2003.
  • [11] Jain R., Tata S., Cloud to Edge: Distributed Deployment of Process-Aware IoT Applications, 2017 IEEE International Conference on Edge Computing (EDGE), Honolulu, HI, 2017, pp. 182-189.
  • [12] Joubert A., Belhadj B., Temam O., Héliot R., Hardware spiking neurons design: analog or digital?, The 2012 International Joint Conference on Neural Networks.
  • [13] Rato R., Coito F., Spike HW Computing, Champalimaud NeuroScience Symposium, 2013, DOI: 10.13140/2.1.3802.2723.
  • [14] Reljan-Delaney M., Wall J., Solving the Linearly Inseparable XOR Problem with Spiking Neural Networks, Computing Conference 2017, 2017.
  • [15] Sourikopoulos I., Hedayat S., Loyez Ch., Danneville1 F., Hoel V., Mercier E., Cappy A., A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology, Frontiers in Neuroscience, 2017.
  • [16] Szczęsny S., Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch, Circuits, Systems and Signal Processing, vol. 36, Issue 7, pp. 2672-2696, 2017.
  • [17] Szczęsny S., High Speed and Low Sensitive Current-Mode CMOS Perceptron, Microelectronic Engineering, vol. 165, pp. 41-51, 2016.
  • [18] Wu X., Saxena V., Zhu K., Balagopal S., A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning, IEEE Transatcions on Circuits and Systems II: Express Briefs, vol. 62, Issue 11, 2015.
  • [19] Zapata M., Balaji U.K., Madrenas J., PSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture, IEEE Third Ecuador Technical Chapters Meeting, pp. 1-6, 2018.
  • [20] Zhang M., Qu H., Belatreche A., Chen Y., Yi Z., A Highly Effective and Robust Membrane Potential-Driven Supervised Learning Method for Spiking Neurons, IEEE Transactions on Neural Networks and Learning Systems, vol. 30, Issue 1, pp. 123-137, 2019.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-7e3c6ac7-5414-4959-8b4f-c4fa7dfbdda0
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.