Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms

• Autorzy: Sugier J.
• Języki publikacji: EN

Abstrakty

EN

The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.

Słowa kluczowe

EN

block cipher; hash function; hardware implementation; loop unrolling; pipelining; FPGA

• Wydawca: Polskie Towarzystwo Bezpieczeństwa i Niezawodności
• Czasopismo: Journal of Polish Safety and Reliability Association
• Rocznik: 2015
• Tom: Vol. 6, No. 2
• Strony: 117--124
• Opis fizyczny: Bibliogr. 17 poz., rys., tab.

Twórcy

autor

Sugier J.

• Wrocław University of Technology, Wrocław, Poland

Bibliografia

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