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Tytuł artykułu

Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.
Słowa kluczowe
Rocznik
Strony
389--396
Opis fizyczny
Bibliogr. 15 poz., wykr., rys., tab.
Twórcy
autor
  • Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India
  • Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India
  • Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India
Bibliografia
  • [1] Chakraborty, Rajat Subhra, and Swarup Bhunia. "HARPOON: an obfuscation-based SoC design methodology for hardware protection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28.10 (2009): 1493-1502.
  • [2] Rajendran, Jeyavijayan, et al. "Fault analysis-based logic encryption." IEEE Transactions on computers 64.2 (2015): 410-424.
  • [3] Chandini, Bandarupalli, and M. Nirmala Devi. "Analysis of Circuits for Security Using Logic Encryption." International Symposium on Security in Computing and Communication. Springer, Singapore, 2018.
  • [4] Hely, David, et al. "Test control for secure scan designs." European Test Symposium (ETS'05). IEEE, 2005.
  • [5] Yang, Bo, Kaijie Wu, and Ramesh Karri. "Secure scan: A design-for-test architecture for crypto chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25.10 (2006): 2287-2293.
  • [6] Cui, Aijiao, Yanhui Luo, and Chip-Hong Chang. "Static and dynamic obfuscations of scan data against scan-based side-channel attacks." IEEE Transactions on Information Forensics and Security 12.2 (2017): 363-376.
  • [7] Karunakaran, Dinesh Kumar, and N. Mohankumar. "Malicious combinational hardware trojan detection by gate level characterization in 90nm technology." Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT). IEEE, 2014.
  • [8] Ali, Sk Subidh, et al. "Novel test-mode-only scan attack and countermeasure for compression-based scan architectures." IEEE transactions on computer-aided design of integrated circuits and systems 34.5 (2015): 808-821.
  • [9] Atobe, Yuta, et al. "Secure scan design with dynamically configurable connection." 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing. IEEE, 2013.
  • [10] Atobe, Yuta, et al. "State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit." 2012 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2012.
  • [11] Roy, Jarrod A., Farinaz Koushanfar, and Igor L. Markov. "Ending piracy of integrated circuits." Computer 43.10 (2010): 30-38.
  • [12] Yasin, Muhammad, et al. "On improving the security of logic locking." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35.9 (2016): 1411-1424.
  • [13] Zhang, Jiliang. "A practical logic obfuscation technique for hardware security." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24.3 (2016): 1193-1197.
  • [14] Karmakar, Rajit, et al. "A new logic encryption strategy ensuring key interdependency." 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID). IEEE, 2017.
  • [15] Yang, Bo, Kaijie Wu, and Ramesh Karri. "Scan based side channel attack on dedicated hardware implementations of data encryption standard." 2004 International Conferce on Test. IEEE, 2004.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-75ec53e3-9d9b-424c-af4c-223af97977da
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