Partial Reconfiguration in the Field of Logic Controllers Design

• Autorzy: Doligalski M. , Bukowiec A.

Identyfikatory

DOI

10.2478/eletel-2013-0042

• Języki publikacji: EN

Abstrakty

EN

The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.

Słowa kluczowe

EN

HCfgPN; UML state machine diagram; Verilog; logic controller

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2013
• Tom: Vol. 59, No. 4
• Strony: 351--356
• Opis fizyczny: Bibliogr. 21 poz., rys., wykr.

Twórcy

autor

Doligalski M.

• Computer Engineering & Electronics Department, University of Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland

autor

Bukowiec A.

• Computer Engineering & Electronics Department, University of Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

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