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SoPC-based DMA for PCI Express DAQ cards

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Języki publikacji
EN
Abstrakty
EN
This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis and multichannel transmission. Performance of the interface has been evaluated on Terasic OVSK board (PCIe Gen2 x4). Target configuration of this interface is based on the Avalon-MM Hard IP for Cyclone V PCIe core and Jungo WinDriver x64 for Windows. A sample speed of 1200 MB/s has been reported for DMA writes to PCIe memory.
Słowa kluczowe
EN
Rocznik
Strony
565--570
Opis fizyczny
Bibliogr. 13 poz., schem., tab., wykr.
Twórcy
  • Institute of Radioelectronics and Multimedia Technology (IRTM), Warsaw University of Technology, Poland
Bibliografia
  • [1] PCI Express Base Specification, rev. 3.0, PCI-SIG, Nov. 2010
  • [2] A. Wójcik, R. Łukaszewski, R. Kowalik, W. Winiecki, “Nonintrusive Appliance Load Monitoring: An Overview, Laboratory Test Results and Research Directions”, Sensors, 2019, 19, 3621
  • [3] A. Wójcik, P. Bilski, R. Łukaszewski, K. Dowalla, R. Kowalik, “Identification of the State of Electrical Appliances with the Use of a Pulse Signal Generator”, Energies, 2021, 14, 673.
  • [4] K. N. Trung, E. Dekneuvel, B. Nicolle, O. Zammit, C. N. Van, G. Jacquemod, “Using FPGA for Real Time Power Monitoring in a NIALM System”, In Proc. 2013 IEEE International Symposium on Industrial Electronics (ISIE), 2013, pp. 1-6
  • [5] Intel Corporation, Modular Scatter-Gather DMA Core, In Embedded Peripherals IP User Guide v. 18.1
  • [6] Intel Corporation, Intel® Quartus® Prime Standard Edition User Guide v. 18.1, Platform Designer
  • [7] Intel Corporation, Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe Solutions User Guide, UG-01110, 2020
  • [8] Intel Corporation, V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide, UG-01154, 2016
  • [9] WinDriver, https://www.jungo.com/st/products/windriver/wd_windows/
  • [10] OpenVINO Stater Kit GT Edition User Manual, available on https://www.terasic.com.tw/
  • [11] L. Rota, M. Caselle, S. Chilingaryan, A. Kopmann, M. Weber, “A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission”, IEEE Transactions on Nuclear Science, vol. 62, no. 3, 2015, pp. 972-976
  • [12] A. Byszuk, J. Kołodziejski, G. Kasprowicz, K. Późniak, W. M. Zabołotny “Implementation of PCI Express bus communication for FPGA-based data acquisition systems”, In Proceedings of SPIE Vol. 8454, 2015
  • [13] L. Boyang, “Research and Implementation of XDMA High Speed Data Transmission IP Core Based on PCI Express and FPGA”, in 2019 IEEE 1st International Conference on Civil Aviation Safety and Information Technology (ICCASIT), Oct. 2019, pp. 408–411.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-72335eb1-87c2-40b0-95a4-c596dd073494
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